Information Technology

IAR Systems delivers advanced trace for RISC-V based applications

01 July 2020

IAR Systems, a supplier of software tools and services for embedded development, has extended the complete development toolchain IAR Embedded Workbench for RISC-V with support for trace as implemented by SiFive Insight, the industry’s first combined pre-integrated trace and debug solution for the freely available, open-specification RISC-V ISA.

In addition to simplifying debugging and helping to enforce good coding practices, trace enables extended testing and proof of code coverage, which is a requirement of several safety standards. By providing live information on code coverage and updates as the program runs, IAR Embedded Workbench enables developers to improve code quality in an efficient way.

IAR Embedded Workbench is a complete development toolchain including the highly optimizing IAR C/C++ Compiler and the feature-rich C-SPY Debugger. The software is complemented by native debugging and trace probes. The debug probe I-jet supports on-chip RAM buffered trace, in addition to fast JTAG/cJTAG/DAP debug and is complemented by the powerful trace probe I-jet Trace, which can livestream trace information for code coverage and profiling purposes.

The new trace features include an updated trace control and status window that provides developers with full control of all active settings and the live trace status of the application. The C-SPY Debugger will decode trace and calculate coverage and profiling as the application executes, populating the respective windows on the fly. This live update enables developers to monitor everything from the available trace buffer to the number of covered instructions. In addition, function profiling makes it possible to see and analyze timing information for the functions in an application, while code coverage analysis shows the percentage of code that has been executed down to single instruction resolution. These combined capabilities offer a non-intrusive and easy-to-use code optimization tool.

Launched in 2019, IAR Embedded Workbench for RISC-V provides excellent optimization technology, helping developers ensure that the application fits the required needs and optimizes the utilization of on-board memory. This also enables companies to aggregate value by adding functionality to an existing platform. To ensure code quality, the toolchain includes the static analysis tool C-STAT, which proves code compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as detect defects, bugs and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.

The current version of IAR Embedded Workbench for RISC-V provides support for RV32 and RV32E 32-bit RISC-V cores and numerous ISA extensions such as C for compressed instructions, and F and D for single-precision and double-precision floating points. Future releases will enhance debug and trace capabilities following RISC-V standardization efforts.

To contact the author of this article, email GlobalSpecEditors@globalspec.com


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