Industrial Electronics

World’s First Eight-Layer 3D IC Wafer Stack to Contain Active Logic

31 August 2015

Tezzaron Semiconductor and its manufacturing subsidiary, Novati Technologies, have announced what they claim is the world’s first eight-layer 3D IC wafer stack that contains active logic. The transistor and interconnect densities per cubic mm are higher than achievable with 2D 14nm silicon fabrication. The result is that the innovation will accelerate high-performance computing and put Moore's Law back on track, potentially saving the industry billions of dollars.

The innovation is expected to accelerate high-performance computing and put Moore's Law back on track, while saving the industry billions of dollars. Source: TezzaronThe innovation is expected to accelerate high-performance computing and put Moore's Law back on track, while saving the industry billions of dollars. Source: TezzaronThe stack represents the densest 3D IC reported to date. Each wafer has 10 layers of copper interconnect supporting high performance CMOS logic—a total of 80 layers of interconnect and eight layers of transistors in a finished stack as thin as a single conventional die.

The wafers were bonded with Ziptronix DBI® technology available from Tessera. Tezzaron’s IC design and fabrication technology creates true 3D IC without wire bonds, copper pillars, bumps, or underfill between the layers. It is not a 3D packaging technology that stacks 2D dies into 3D assemblies. Instead, the wafers are bonded directly, wafer-to-wafer, producing devices that can be finished to the same thickness as conventional 2D dies for excellent electrical, thermal, and mechanical performance.

Each wafer in the finished stack is only 20μm thick. This allows vertical interconnect through the stack to be extremely dense and electrically unobtrusive, capable of carrying very small and fast signals. Tezzaron uses 1.2μm diameter tungsten SuperContacts rather than conventional copper TSVs. SuperContacts can be used at a 2.4μm pitch with no required keep-out zones near active transistors, so densities can exceed 170 thousand vertical connections per square mm. This is 350 times denser than the state-of-the-art copper TSV vertical interconnect.

Questions or comments on this story? Contact engineering360editors@ihs.com

Related Links:

http://www.tezzaron.com



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