Semiconductor Equipment

New entry to PCIe testing field offers quicker results, greater accessibility

19 November 2022

Regular readers of Electronics360 may recall the recent report on PCI Express testing, a field often characterized by complex test equipment and populated with engineers with deep expertise and knowledge. A new product from test and measurement solutions manufacturer Tektronix aims to widen the accessibility of that field, with capabilities designed to minimize the need for senior-level engineers to perform link health evaluations of their designs.

The TMT4 Margin Tester is geared at transforming time-to-market, cost and accessiblity of PCIe testing. Source: Tektronix Inc.The TMT4 Margin Tester is geared at transforming time-to-market, cost and accessiblity of PCIe testing. Source: Tektronix Inc.Tektronix said the combination of plug-and-play set up and an easy-to-use interface allows results from the TMT4 Margin Tester to be delivered in minutes instead of the costly hours (or even days) of set up and testing typically required for PCIe design and validation. The product is geared to PCIe Gen Gen 3 and Gen 4 motherboards, add-in cards and system designs, enabling “engineers at all levels of experience to evaluate the health of transmitter (Tx) and receiver (Rx) links faster than ever.”

The TMT4 features multilane testing capabilities of up to 16 lanes across PCIe presets 0-9, using a single standard connector — thus reducing the number of connection changes needed to perform testing. Tektronix says the device can perform PCIe device testing across up to 160 combinations of lanes and presets in as little as 20 minutes at Gen 4 speeds. The company also points out that the speed and versatility of the device make it a fit for conducting earlier and more frequent evaluation of board- or system-level link health during design and validation.

It should be noted that the product is not a standalone solution: The TMT4 is intended to complement full validation and compliance testing systems consisting of oscilloscopes and bit error ratio testers (BERTs). The idea behind the new device is not to replace traditional equipment, but to uncover issues earlier in the design process prior to an in-depth examination.

Features include quick scan and custom scan modes, full Tx/Rx protocol capability and link training parameter visibility. A variety of adapters supports the majority of common PCIe form factors for connecting to motherboard and add-in card devices under test, including CEM, M.2, U.2 and U.3.



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