Aerospace

4 reasons to use RISC-V for aerospace and defense applications

29 April 2019
Antmicro is an embedded technology company that works with early adopters of RISC-V like aerospace and defense company Thales SA to advance the open ISA’s adoption. Source: Antmicro

As aerospace and defense firms look toward developing future air and space platforms, they are making decisions about which hardware and software elements to use in their designs.

One significant design choice is the underlying instruction set architecture (ISA) that defines the interface between the software and hardware for a computer processor.

RISC-V soft CPU cores can be implemented on FPGA boards like Microsemi’s 25K LUT IGLOO2 RISC-V Creative Development Board. Source: MicrosemiRISC-V soft CPU cores can be implemented on FPGA boards like Microsemi’s 25K LUT IGLOO2 RISC-V Creative Development Board. Source: Microsemi

Among the options for ISAs are familiar commercial architectures like Intel’s x86 ISA that dominates the desktop and server markets and the ARM architecture common in mobile devices like smartphones.

But these ISAs are the proprietary intellectual property (IP) of their owners. Any developers designing new processors based on these commercial ISAs may pay steep fees to the owners.

A relatively new ISA called RISC-V has emerged as an open source alternative to commercial ISAs.

RISC-V is an extensible, widely available, modern ISA designed to support efficient, high-performance computing. Although RISC-V is new, it is experiencing rapid adoption thanks to its open license, efficient design and burgeoning development resources like emulators, debuggers and operating system support. RISC-V may represent a viable option for chip designs in many industries, but may be particularly well suited for aerospace and defense applications for at least four reasons.

1. Verifiable security

Aerospace applications – particularly military and defense deployments – require trusted components. To receive approval for use, chips must be verifiably free of malicious code that could be used to harm or sabotage an operation.

SiFive’s HiFive1 RISC-V development board features the Freedom E310 RISC-V SoC. Source: Gareth Halfacree / CC BY-SA 2.0SiFive’s HiFive1 RISC-V development board features the Freedom E310 RISC-V SoC. Source: Gareth Halfacree / CC BY-SA 2.0

When it comes to verification, RISC-V’s open ISA may offer an advantage over closed architectures like x86 or ARM. Since RISC-V is open, companies can choose to reveal the complete register-transfer level (RTL) source code of their RISC-V IP cores to designers without running into restrictions around commercial ISA licensing and protected IP. Designers can then perform a full inspection of the RTL, providing confirmation of no malicious intent and establishing trust.

As a result, RISC-V seems well suited for sensitive applications where security and confidentiality are paramount, like secure data communications, as well as for high risk military applications where authenticity and reliability are critical.

2. Frozen base specification for long-term stability

Aerospace and defense platforms often have service lives measured not in months or years, but in decades. The Boeing B-52 Stratofortress, Lockheed C-130 Hercules and Boeing KC-135 Stratotanker have all been in service with the U.S. Air Force for more than 60 years.

RISC-V presents an architecture well suited for extended service life because the base RISC-V specifications and instruction set are frozen. Designers can be reasonably certain that the platform they are designing around will remain stable for a long time. Software created for RISC-V hardware that exists now will continue to run on future RISC-V chips. That means code can be validated once and then reused on future generations of RISC-V processors.

Closed, commercial ISAs typically lack this long-term stability. They were not specifically designed for extensibility, so modifications that include new instructions or extensions often require software to be rebuilt from source code to avoid obsolescence.

3. Designed for extensibility and innovation

RISC-V’s four base instruction formats are each 32 bits in length, but the ISA encoding scheme supports extensions that are any combination of 16-bit instruction parcels, including 16, 32, 48 bits, etc. RISC-V instruction sets supporting 16, 32 and 64-bit address spaces are defined and a 128-bit variant is already outlined to support future advances in memory technology. Source: RISC-V FoundationRISC-V’s four base instruction formats are each 32 bits in length, but the ISA encoding scheme supports extensions that are any combination of 16-bit instruction parcels, including 16, 32, 48 bits, etc. RISC-V instruction sets supporting 16, 32 and 64-bit address spaces are defined and a 128-bit variant is already outlined to support future advances in memory technology. Source: RISC-V Foundation

Aerospace platforms often have long service lives because of the high cost of designing new platforms from scratch. Although complete redesigns are cost prohibitive, it is common to upgrade the capabilities of existing platforms by incorporating technology advances in updated models.

For example, the avionic systems of military aircraft, including communications, navigation and tactical sensors must be kept current to match or exceed the capabilities of potential adversaries. The aging B-52, C-130, and KC-135 fleets all have been through refurbishment and modernization programs to achieve this goal.

RISC-V offers designers a foundation to build on for scenarios like these. RISC-V is designed for extensibility in addition to stability. The base instruction set is frozen, but additional capabilities can be added as extensions without affecting the functionality of existing software. Custom accelerators that mix and match the base instruction set with specialized extensions can be tailored to specific applications.

The open RISC-V ISA license grants developers the freedom to customize chip designs as they see fit. Processor microarchitectures can be redesigned and upgraded for higher efficiency. Hardware can be designed to meet specific goals, like low power consumption, maximum performance or secure data processing.

4. Open source and no licensing fees

Commercial ISAs are protected intellectual property. To build a new chip around the ARM architecture, for example, a developer typically must pay upfront fees as well as per-chip royalties. The RISC-V ISA, in contrast, is open source making it available to anyone to use as the underlying architecture for processor designs.

At the same time, hardware designs built on RISC-V need not remain open source. Developers may choose to keep their designs as proprietary intellectual property to be commercialized and monetized at their discretion. The RISC-V Foundation – the non-profit corporation that guides the development of the RISC-V ISA – encourages both open source and commercial implementations of the RISC-V ISA.

Further reading

RISC-V User-Level and Privileged ISA Specifications

To contact the author of this article, email eric.olson@ieeeglobalspec.com


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