Electronics and Semiconductors

Industry One Step Closer to Nanoscale EUV Manufacturing - Imec and Cadence Validate First 3nm Test Chip Tapeout

22 March 2018

Imec and Cadence researchers have developed electronic industry's first 3nm tapeout. Source: Imec & CadenceImec and Cadence researchers have developed electronic industry's first 3nm tapeout. Source: Imec & CadenceWith the validation of the first 3nm test chip tapeout by imec and Cadence, the electronics industry is one step closer to realizing nanoscale EUV manufacturing.

Imec and Cadence announced that their long-term partnership has produced the industry’s first 3nm test chip tapeout using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec is a world-leading research and innovation hub in nanoelectronics and digital technologies. Cadence Design Systems, Inc. is a leading provider of EDA solutions and the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. Their tapeout project was focused on advancing 3nm chip design using common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

The Cadence Innovus Implementation System used to create the tapeout has a massively parallel physical implementation system that enables engineers to rapidly deliver high-quality designs with optimal power, performance and area (PPA) targets to market. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X.

Post place and route layout of 21 nm pitch metal layers in 3nm tapeout test chip. Source: Imec & CadencePost place and route layout of 21 nm pitch metal layers in 3nm tapeout test chip. Source: Imec & CadenceEUV and 193i lithography rules were tested in the project to provide the required resolution, while providing PPA comparison under two different patterning assumptions. “Imec Presents Patterning Solutions for N5-equivalent Metal Layers” provides more details on their EUV and 193i technology. “As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.”

Nanoscale design and fabrication technology are poised to overcome the limitations of microscale electronics and provide higher speeds and performance for computers, mobile communications, sensors and other electronic products. Obstacles to fully implementing nanoelectronics remain such as overcoming interconnection problems and maintaining yields as design shrink.

For more information on this development see:
Imec and Cadence Tape Out Industry’s First 3nm Test Chip



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