Industrial Electronics

At 2018 IEEE ISSCC: Achieving 120 Gbps Wireless Transmission with New CMOS Chip

13 February 2018

This CMOS wireless transceiver chip achieved wireless communication at 120 Gbps. Source: Tokyo Institute of TechnologyThis CMOS wireless transceiver chip achieved wireless communication at 120 Gbps. Source: Tokyo Institute of Technology

Tokyo Institute of Technology and Fujitsu Laboratories Ltd. have developed a CMOS wireless transceiver chip that can process signals at high speeds across a broad range of frequencies, from 70 to 105 gigahertz (GHz), using their own bandwidth-increasing technology. With this development, the researchers achieved wireless transmission speeds of 120 gigabits per second (Gbps) — the world’s fastest.

The new CMOS wireless transceiver chip broadens the band of transceiver circuits by splitting data signals in two, converting them to different frequency ranges and then recombining them. Each signal is modulated into a band 17.5-GHz wide and demodulated, with the low-band signal occupying the 70.0-87.5 GHz range and the high-band signal occupying the 87.5-105.0 GHz range. This technology enables high-quality signal transmission over an ultra-wideband signal 35 GHz wide. CMOS wireless transceiver chip has carrier generation circuits built in for the 70-GHz and 105-GHz carrier signals required to use this technology.

Conventionally, the signal quality was degraded by higher harmonics contained by the carrier generation circuit, but the new harmonic suppression technology resolved this problem. The signal quality required for multi-level modulation of 16-QAM has been achieved by using a lower-order multiplication technique and combining many stages of amplifier circuits and the built-in higher-harmonic-suppressing filter. Tokyo Tech developed technologies for improving transceiver performance and broadening the band, while Fujitsu Laboratories was responsible for module technology.

A paper on this research, A 120Gb/s 16QAM CMOS Millimeter-Wave Wireless Transceiver, will be presented during Session 9 of the 2018 IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco.

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