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3-D Chip Uses Carbon Nanotubes and Data Storage to Improve Bandwidth Bottlenecks

05 July 2017

The carbon nanotubes and RRAM cells are built vertically over one another making a dense 3-D computer architecture with interleaving layers of logic and memory. Source: MIT The carbon nanotubes and RRAM cells are built vertically over one another making a dense 3-D computer architecture with interleaving layers of logic and memory. Source: MIT Researchers at Stanford and MIT have developed a new prototype chip that uses multiple nanotechnologies with a new computer architecture. The chip helps overcome current bottlenecks limiting the ability of computers to process mass amounts of data.

Computers consist of different chips that are used for computing, data storage, connections between the two and more. As advanced applications are increasing the amount of data that these computers need to process, the various chips are creating a communication bottleneck. Furthermore, silicon transistors are no longer improving at the historic rate that they have for decades (known as Moore’s law).

The new prototype chip seeks to reverse these trends. Instead of relying on silicon-based devices, the chip uses carbon nanotubes — sheets of 2-D graphene formed into nanocylinders — and resistive random-access memory (RRAM) cells, a nonvolatile memory that operates by changing the resistance of a solid dielectric material.

Researchers integrated more than 1 million RRAM cells and 2 million carbon nanotube field-effect transistors to create what they claim is the most complex nanoelectronic system ever made with emerging nanotechnologies.

How They Did It

The RRAM and carbon nanotubes are built vertically over one another, making a 3-D computer architecture with interleaving layers of logic and memory. Inserting ultra-dense wires between the layers, the 3-D architecture promises to address the communication bottleneck, MIT says.

“Circuits today are 2-D, since building conventional silicon transistors involves extremely high temperatures of over 1,000 degrees Celsius,” said Max Shulaker, a member of MIT’s Microsystems Technology Laboratories. “If you then build a second layer of silicon circuits on top, that high temperature will damage the bottom layer of circuits.”

By contrast, the carbon nanotube circuits and RRAM memory can be fabricated at temperatures below 200 degrees Celsius, meaning they can be built up in layers without harming the circuits beneath.

“The devices are better: Logic made from carbon nanotubes can be an order of magnitude more energy-efficient compared to today’s logic made from silicon, and similarly, RRAM can be denser, faster, and more energy-efficient compared to DRAM,” said Philip Wong, an MIT Ph.D student working on the project.

The system also address interconnects within and between the chips to improve the device.

MIT demonstrated the technology by having the carbon nanotubes act as a sensor. They placed more than 1 million carbon nanotube-based sensors and then used the sensors to detect and classify ambient gases.

The chip was able to measure each of the sensors in parallel and then write directly into its memory, generating an impressive bandwidth. MIT says the 3-D integration is the most promising approach to continuing the technology scaling path set forth by Moore’s law, allowing an increasing number of devices to be integrated per unit volume.

The next steps involve improving the nanotechnologies while exploring the new 3-D computer architecture. For example, the devices could be used to detect signs of disease by sensing particular compounds in a patient’s breath.

“The technology could not only improve traditional computing, but it also opens up a whole new range of applications that we can target,” said Max Shulaker, an assistant professor of electrical engineering and computer science at MIT. “My students are now investigating how we can produce chips that do more than just computing.”

To contact the author of this article, email Peter.Brown@ieeeglobalspec.com


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