Each of the devices’ two independent buffer channels offers up to eight low-skew outputs. Effective isolation between channels minimizes noise coupling. Alternating current characteristics, such as propagation delay, are matched between channels.
Delivering up to 50% lower power than comparable competitive devices, IDT’s dual-channel buffers allow board designers to reduce power consumption while maintaining clock performance. The buffers also enable engineers to move to lower supply rails in support of deeper submicron silicon processes.
The devices enable two different signals to be buffered while remaining synchronous with one another. One channel can be used for a clock; the other can be used for a synchronization signal or data, as applicable in device clock and SYSREF signal distribution in JESD204B applications. The power reduction allows higher system packing densities, saves cost in the power supply and cooling, and delivers lower power footprints.
The buffers’ low additive phase jitter, high spurious attenuation and low clock output skew are combined with high clock frequency support. Their compatibility with LVDS devices make them easy to use, and they are compatible in pin and function to equivalent industry standard 2.5 V and 3.3 V parts from IDT.