Samsung Electronics is now mass producing the industry’s first 10-nanometer (nm) class, 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips, as well as the modules derived from them.
Because DDR4 is becoming one of the most widely produced memory types for personal computers and IT networks in the world, Samsung’s 10-nm class DRAM was intended to accelerate the industry’s shift to DDR4 products even more.
After overcoming technical challenges in DRAM scaling using currently available ArF (argon fluoride) immersion lithography, the company finally released its DRAM chips on Tuesday.
“Samsung’s 10-nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10-nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”
Samsung’s leading-edge 10-nm-class 8Gb DDR4 DRAM improves the wafer productivity of 20-nm 8Gb DDR4 DRAM by more than 30%. It supports a data transfer rate of 3,200 megabits per second, and the new modules produced from the 10-nm-class DRAM chips consume 10% to 20% less power, compared to their 20-nm process-based equivalents. These factors will improve the design efficiency of next-generation, high-performance computing systems and other large enterprise networks, and be used for the PC and mainstream server markets.
The new DRAM is a result of Samsung’s recent technological innovation advancements, which include improvements in proprietary cell design technology, QPT (quadruple patterning technology) lithography and ultra-thin dielectric layer deposition.
When it comes to DRAM, each cell requires a linked capacitor and transistor, unlike in NAND flash memory where each single cell only has a transistor. In the case of the new 10-nm-class DRAM, engineers had to figure out how to stack a very narrow cylinder-shaped capacitor that stores large electric charges on top of a few dozen nanometer-wide transistors, in order to create over eight billion cells.
Samsung successfully created the new 10-nm-class cell structure by using its proprietary circuit- design technology and quadruple patterning lithography. QPT enables the use of existing photolithography equipment. Samsung also employed a refined dielectric layer deposition technology, which allowed for even more performance improvements.
The engineers applied ultra-thin dielectric layers to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, which created enough capacitance for higher cell performance.
Samsung also hopes to introduce a 10-nm-class mobile DRAM solution with high density and speed later this year.