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Semiconductors and Components

IEDM Divulges Advances in Wide Bandgap Devices

05 February 2016

Recent advances in device structure and process technology has significantly improved the performance of wide bandgap (WBG) power devices, especially those based on gallium nitride (GaN) and silicon carbide (SiC) technologies. These advances are pushing the adoption of these power devices at very high voltages, high temperature and high power applications. As a result, the market for both SiC and GaN power devices has grown decently in the last few years. According to technology analyst Yole Developpement, the SiC devices (diodes and transistors) market was worth over $133 million in 2014. The rate at which these devices are being adopted in photovoltaic (PV) inverters and electric, including hybrid, vehicles, the SiC devices market is projected to treble by 2020, reaching $436 million. Likewise, the market analyst is projecting over $300 million for GaN power devices by 2020.

Key barriers for broader adoption of these devices include high cost, high temperature, reliability, multi-sourcing and integration. Some of these challenges were addressed in a special focus session on WBG devices at the recent International Electron Devices Meeting (IEDM) in Washington D.C. There were eight invited papers in this focus session. A paper titled “SiC- and GaN-based power devices: Technologies, Products and Application,” by STMicroelectronics, provided a good perspective in terms of its developments at ST and its adoption in the marketplace.

In 2014, ST unveiled its first 1200 V SiC MOSFET capable of operating up to a junction temperature of 200° C. Its on-resistance was 80 mΩ. Ongoing tests show that no significant changes are observed in the behavior of the SiC MOSFET even after 3,000 hours of operation at 200° C. Plus, it overcomes all JEDEC reliability tests with zero failures. This has prompted the manufacturer to develop higher voltage SiC MOSFETs, as well as 650 V version. The roadmap revealed in this paper indicates that ST is now developing SiC MOSFETs at 1700 V with plans to release 3300 V and 6500 V devices in 2016. In addition, targeting inverters in hybrid and electric cars, ST is also developing SiC MOSFETs in the 650 – 900 V range.

Besides improving the output characteristics of its 650 V SiC MOSFET, ST engineers have also improved the device process to achieve a high carrier mobility of 40-50 cm2/Vs. Concurrently, advances in device process shows that the normalized on-resistance of the 650 V SiC MOSFET remains basically constant in the range between room temperature and 200° C. The study reveals that the specific on-resistance of these devices remains below 4 mΩ×cm2 even at 200° C junction temperature. Work is underway to improve layout and process to further lower the specific on-resistance to as low as 2 mΩ×cm2.

Advances in device process has enabled STMicroelectronics to develop a 650 V SiC MOSFET with low on-resistance that remains basically constant in the range between room temperature and 200 °C. (Source: IEDM 2015)Advances in device process has enabled STMicroelectronics to develop a 650 V SiC MOSFET with low on-resistance that remains basically constant in the range between room temperature and 200 °C. (Source: IEDM 2015)

On the GaN front, ST is developing a normally-off 25 A, 650 V GaN-on-Si HEMT with specific on-resistance of 4 mΩ×cm2. For GaN power switches, according to ST’s paper, the evolution of cost/performances ratio is expected to occur with manufacturing volumes, which will happen when mass production moves to 8-inch silicon substrates.

STMicroelectronics identifies applications that will tap the benefits of SiC and GaN power devices. (Source: IEDM 2015)STMicroelectronics identifies applications that will tap the benefits of SiC and GaN power devices. (Source: IEDM 2015)

ST foresees that SiC power devices will dominate applications at high power/high temperature/high voltage while GaN will play a larger role in the other domains. Last but not least, a widespread use of SiC and GaN power devices requires a strong effort to improve the cost/performances ratio.

Vertical Devices, Larger Substrates

Similarly, development issues for fabrication of vertical GaN power devices were reviewed by Tetsu Kachi of Toyota Central R&D Labs Inc. in a paper titled “State-of-the Art GaN Vertical Power Devices.” For over a decade, the focus has been on lateral GaN structures on silicon substrates. But, some progress has also been made on vertical structure as the GaN substrate quality has been improved lately. Using high quality GaN substrates, Kachi’s team has demonstrated a vertical GaN transistor on a GaN substrate. However, the uniformity of the quality and the size are still an issue. Work is underway to address these issues.

Another player in the vertical GaN arena is Massachusetts Institute of Technology (MIT). In collaboration with Cambridge Electronics Inc. (CEI), MIT researchers are in the process of developing a new generation of vertical GaN diodes on silicon substrates to take advantage of the high power density of vertical structure at the cost-point of silicon. One of the main challenges for these devices is the high off-state leakage current. MIT has addressed this problem by passivating a sidewall with a novel plasma-based surface treatment. As a result, according to MIT’s paper titled “Advanced Power Electronic Devices Based on Gallium Nitride (GaN), vertical GaN power diodes on silicon were fabricated with lower off-state leakage current levels than lateral devices. Although this vertical technology is still not ready for insertion into commercial systems, it may play an important role in the future, said MIT.

Concurrently, Belgium’s research group Imec is pushing the fabrication of GaN on 200-mm (8-inch diameter) silicon substrates. Earlier the thermal and lattice mismatch between GaN and silicon substrate has limited its scalability to larger areas (200-mm and beyond). The current trend is using 150-mm (6-inch diameter) substrates. In this invited paper titled “200mm GaN-on-Si epitaxy and e-mode Device Technology,” Imec researchers D. Marcon, Y.N. Saripalli, and S. Decoutere talk about three types of high-voltage buffers for GaN on 200-mm silicon epitaxy. Their analysis shows that both superlattice (SL) and interlayer (IL) approaches reduce the density of slip lines and cracks significantly with respect to the step graded buffer approach while achieving lower leakage at higher voltages.

Using these buffers, the researchers have developed two device architectures, namely recessed gate MISHEMT and p-GaN HEMT. The study found that despite improvements in recessed gate MISHEMT, it is limited in obtaining Vth above 1.5 V and Ron below 10 Ω·mm, and low positive bias thermal instability (PBTI). On the other hand, the same researchers found that with optimized e-mode p-GaN HEMT technology, it is possible to achieve Vth larger than 2 V (2.1 V at Ids = 0.1 mA/mm), Ron =7 Ω·mm and Idsat @ Vgs=10 V > 0.4 A/mm and no hysterisis. Furthermore, the study shows that the gate leakage problem can be solved with an optimized process. Thus, demonstrating p-GaN HEMT devices with less than 10 nA/mm gate leakage at Vgs = +12 V.

Schematic cross- section of (a) a recessed gate MISHEMT and (b) a p-GaN HEMT.  (Source: IEDM 2015)Schematic cross- section of (a) a recessed gate MISHEMT and (b) a p-GaN HEMT. (Source: IEDM 2015)

Similar efforts are also underway at France’s CEA-Leti. In a paper titled “From Epitaxy to Converters Topologies What Issues for 200 mm GaN/Si?," CEA-Leti researchers discussed issues pertaining to the growth of GaN epitaxial layers on 200 mm silicon substrate. With improvements in buffer layers and leakage current, the paper disclosed development of 650 V normally-on and normally-off MIS gate HEMT transistors at CEA-Leti.

Borrowing ideas from silicon, Kyoto Institute of Technology’s researcher Daisuke Ueda investigates novel structures for high voltage GaN based power transistors. The results were revealed in the paper titled “Renovation of Power Devices by GaN-based Materials.”

Performance benefits of using high-K gate dielectric techniques were disclosed by Intel researchers in a paper titled “High-K Gate Dielectric Depletion-Mode and Enhancement-Mode GaN MOS-HEMTs for Improved OFF-State Leakage and DIBL for Power Electronics and RF Applications.” In this paper, the researchers presented off-state leakage and drain induced barrier lowering (DIBL) results for depletion-mode and enhancement-mode GaN MOS-HEMTs.

From applications standpoint, engineers at HRL Laboratories showed that GaN’s figure of merit (FOM) for soft-switching is 9X better than silicon superjunction MOSFET. Plus, using this FOM, the engineers demonstrated that GaN devices in 400 V soft-switching converters are predicted to switch beyond 100 MHz. These results were revealed in a paper titled “Increasing the Switching Frequency of GaN HFET Converters.



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