Samsung Electronics has begun mass producing the industry’s first 4-gigabyte DRAM package based on its High Bandwidth Memory (HBM2) interface, for use in high performance computing, advanced graphics and network systems.
The company’s HBM interface will offer DRAM performance that is more than seven times faster than the current DRAM performance limit, which allows for faster response times needed in high-end computing tasks like parallel computing, graphics rendering and machine learning.
“By mass producing next-generation HBM2 DRAM, we can contribute much more to the rapid adoption of next-generation HPC systems by global IT companies,” says Sewon Chun, senior vice president, Memory Marketing, Samsung Electronics. “Also, in using our 3D memory technology here, we can more proactively cope with the multifaceted needs of global IT, while at the same time strengthening the foundation for future growth of the DRAM market.”
The 4GB HBM2 DRAM uses Samsung’s 20-nanometer process technology and advanced HBM chip design and piggybacks on the company’s introduction of a 128GB 3D TSV DDR4 registered dual inline memory module (RDIMM).
How it’s done
The 4GB HBM2 package was created by stacking a buffer die at the bottom and four 8-gigabit (GB) core dies on top which were then interconnected by TSV holes and microbumps. Since a single 8GB HBM2 die contains over 5,000 TSV holes – more than 36 times that of an 8GB TSV DDR4 die – it provides a significant improvement in data transmission performance compared to typical wire-bonding based packages.
The new DRAM package comes equipped with 256GBps of bandwidth which, according to Samsung is the equivalent of more than a seven-fold increase over the 36GBps bandwidth of a 4GB GDDR5 DRAM chip (which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips).
Samsung will increase production volume of its HBM2 DRAM over the course of the next year and plans to expand its line-up of HBM2 DRAM solutions.