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Power Semiconductors

Atomically-Thin Transistor Slashes Power Dissipation

10 December 2015

Aiming to cut power consumption of transistors significantly, researchers at the University of California Santa Barbara (UCSB), in collaboration with Rice University, have developed a new transistor structure that switches at only 0.1 volts. As a result, it reduces power dissipation by almost 90% as compared to leading-edge silicon MOSFETs.

Tunnel field-effect transistor (TFET) uses layered 2D material molybdenum disulphide (MoS2) as the current carrying channel placed over germanium (Ge) as the source electrode.Tunnel field-effect transistor (TFET) uses layered 2D material molybdenum disulphide (MoS2) as the current carrying channel placed over germanium (Ge) as the source electrode.Under the guidance of Prof. Kaustav Banerjee of Electrical and Computer Engineering, the UCSB team has employed the quantum mechanical phenomenon of band-to-band tunneling to design a tunnel field-effect transistor (TFET) with sub-60 mV per decade of subthreshold swing. "We restructured the transistor's source to channel junction to filter out high energy electrons that can diffuse over the source/channel barrier even in the off state, thereby making the off state current negligibly small," states Banerjee.

The TFET uses a layered 2D material called molybdenum disulphide (MoS2). As the current-carrying channel placed over a highly doped germanium (Ge) as the source electrode, MoS2 offers an ideal surface and thickness of only 1.3 nm. As a result, the vertical heterostructure provides a unique source-channel junction that is strain-free, has a low barrier for current-carrying electrons to tunnel through from Ge to MoS2 through an ultra-thin (~0.34nm) van der Waals gap, and a large tunneling area, according to the UCSB researchers.

In fact, the new TFET combines the best of 3D and 2D materials to achieve a unique heterostructure. “We have engineered the thinnest-channel sub-thermionic transistor ever made,” explains Banerjee. Their atomically-thin and layered semiconducting channel tunnel FET (or ATLAS-TFET) is the only planar architecture TFET to achieve sub-thermionic subthreshold swing (~30 mV/decade at room temperature) over four decades of drain current, and the only one in any architecture to achieve so at an ultra-low drain-source voltage of 0.1 V, asserts Banerjee.

At UCSB, Banerjee's Nanoelectronics Research Lab includes Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang and Stephan Kraemer, as well as Yongji Gong and Pulickel Ajayan of Rice University. The results of this work were first published in the September 30th issue of the weekly journal of science Nature.



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