Synopsys has announced the HAPS-80 FPGA-Based Prototyping Systems, part of its end-to-end Prototyping Solution. The HAPS-80 systems deliver up to 100 MHz multi-FPGA performance and high-speed time-domain multiplexing (HSTDM) technology. HAPS-80 with ProtoCompiler design automation and debug software uses the latest Xilinx Virtex UltraScale VU440 devices with 26-million-ASIC-gates capacity per FPGA, supporting designs to over 1.6 billion ASIC gates. The HAPS hardware and ProtoCompiler software combination accelerates software development, hardware/software integration and system validation.
ProtoCompiler software has built-in knowledge of the HAPS system architecture, which automates partitioning and enables an average time to the first prototype of less than two weeks and subsequently compile iterations in hours compared to non-integrated prototypes. The software takes advantage of HAPS-80's new HSTDM capabilities to select the optimum mix of pin-multiplexing schemes to best match the design under test. The integrated HAPS-80 solution delivers performance of up to 300 MHz for single FPGA designs, up to 100 MHz for multi-FPGA without pin-multiplexing and up to 30 MHz for multi-FPGA with new proprietary high-speed pin-multiplexing. The increased system performance of the HAPS-80 systems enables OS booting to the command prompt in less than a minute, allowing designers to probe and initialize device hardware such as CPU, timers and UARTs. HAPS-80 also enables at-speed operation of real world I/O.
Unified Compile with VCS simulation and Unified Debug with Verdi debug—part of Synopsys' Verification Continuum platform—eases migration between simulation, emulation and prototyping that saves months of design and verification bring-up time.
ProtoCompiler's automated RTL-to-FPGA image timing-driven flow delivers the highest prototype performance and quickest turnaround times compared to the previous generation. It enables the creation of prototypes with an optimum multi-FPGA design partition, lowest pin-multiplexing ratios, optimized synthesis and guided FPGA place and route.
HAPS-80 systems deliver superior debug visibility and automation through HAPS Deep Trace Debug Gen4 (DTD4) technology, providing the ability to capture more than 1000 debug signal bits per FPGA at speed. Debug data acquisition, debug storage memory and dedicated debug routes are built into the HAPS-80 systems and automatically inserted by ProtoCompiler to ensure that minimally invasive debug is always available to the user. HAPS DTD4, in combination with Synopsys Verdi debug software, helps designers rapidly visualize complex design behavior in the context of the original RTL source for a simulator-like experience, reducing debug time by up to 50%. In addition, the integration of HAPS and ProtoCompiler with the Verification Continuum's Unified Compile technology eases migration between Synopsys VCS simulation, ZeBu emulation and HAPS prototyping to save up to months of design and verification time.
The host connectivity enables hybrid prototyping, global accessibility and prototyping farm use modes. The UMRBus provides seamless connection between HAPS-80 systems and Synopsys' Virtualizer-based virtual prototypes to create an integrated hybrid prototyping environment for early software development and hardware/software integration. In addition, HAPS-80 is backward compatible with HAPS-70, enabling designers to reuse existing systems and hardware accessories. The native Ethernet connection in the HAPS-80 system enables global system accessibility via connection to a standard Ethernet. The HAPS-80 solution supports multi-design mode to execute multiple designs simultaneously across HAPS systems in an enterprise configuration, delivering the highest prototype utilization and a greater return on investment for multiple project usage.
The HAPS-80 FPGA-based prototyping systems and ProtoCompiler software are available.
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