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Semiconductors and Components

Xilinx Completes 16nm FinFET Multiprocessor SoC Design

03 July 2015

Xilinx Inc. has completed its chip design for its next generation Zynq programmable multiprocessor system-on-chip (MPSoC) using Taiwan Semiconductor Manufacturing Co. (TSMC)’s 16nm FinFET process.

The MPSoC is targeted at next generation embedded vision systems such as industrial machine vision, surveillance and advanced driver assist systems (ADAS). Specifically to ADAS, Xilinx says the chip includes expanded memory for video buffering and enough horsepower to enable real-time safety-critical countermeasures. The field programmable gate array (FPGA) giant also says the design of the chip was with automotive ISO-26262 standard, which defines functional safety for automotive equipment applicable throughout the lifecycle of all automotive electronic and electrical safety-related systems, in mind to allow for custom design changes as ADAS evolves.

Tom Hackenberg, Tom Hackenberg, principal analyst for embedded processors at IHSTom Hackenberg, principal analyst for embedded processors at IHSsays the multiprocessor SoC is one of the first processors (not just the first FPGA) to be built on 16nm FinFET technology. It is also one of the few chips that is a 3D packaged IC meaning disparate subsystems—logic, memory and analog—are stacked on top of each other instead of the typical monolithic design, he says.

“Historically, FPGAs have been one or two process nodes behind the leading performance processors, now they are at the cutting edge,” Hackenberg says. As a result of this design, a smaller area footprint even with more subsystems, lower power and greater performance per watt is generally an advantage to all markets, he says.

The Zynq MPSoC combines seven programmable processors including a quad-core 64-bit ARM Cortex-A53 application processing unit (APU), a dual-core 32-bit ARM Cortex real time processing unit (RTPU) and an ARM Mali-499 graphics processing unit (GPU). The chip also features a host of peripherals, safety and security features and advance power management, Xilinx says.

While multicore processing has been a strong trend in the last decade, Hackenberg says this is the first device to integrate this level of asymmetric complexity. “Not all applications need this level of complexity, but for those that do, such as Internet gateways, machine vision applications or advanced driver assist systems, this level of integration is a tremendous boost to design simplicity and accelerating time to market,” he says.

Next Evolution of System Integration

The complexity of the Zynq MPSoC represents a major step toward the future of how chip-level integration may enable new applications to come forward.

Whereas many applications can today be solved by a simple microcontroller or digital signal processor (DSP) or an inexpensive applications processor, newer technologies such as ADAS, wearables, wireless gaming platforms and the Internet of Things (IoT) for medical diagnostic or home medical gateway would need this type of integration.

“There are numerous IoT, wireless and automotive applications where this would represent a sledgehammer when you just want to drive a nail,” Hackenberg says. “But we know that this chip represents the next evolution of system integration to reduce design costs and design complexity for the board or system level designer.”

That means there could be enough savings in design costs to do something new or never before attempted or it might be savings in power, size, area or even just monetary cost for those trying to replace several different components with one MPSoC, Hackenberg says.

As such, this is not going to be the type of chip that will run small battery operated sensors that will proliferate with the IoT infrastructure or a chip that will show up in simple home automation or cheap fitness brands. However, as IoT applications need video and voice content—such as next generation Glass, video game interfaces, customized security controller or home medical gateway—this might be just the solution, Hackenberg says.

Questions or comments on this story? Contact engineering360editors@ihs.com

Related links:

www.xilinx.com

IHS Semiconductors & Components

News articles:

Xilinx and China Mobile Team for 5G NGFI

Xilinx, TSMC Team for 7nm Process Technology

Singapore Transportation Authority to Use Xilinx SoCs

Xilinx Tips 16nm FinFET FPGAs

Xilinx Begins Volume Production of 20nm FPGAs

To contact the author of this article, email Peter.Brown@ieeeglobalspec.com


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