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Semiconductors and Components

Silicon Nanowire Remains Favorite to Replace FinFET

16 June 2015

Silicon-based nanowire transistors (NWTs)—otherwise known as gate-all-around transistors—are getting ready to replace FinFETs at the 7nm or 5nm integrated circuit (IC) manufacturing nodes, according to experts in the field.

Although the alternatives of vertical versus lateral orientation and silicon, germanium, carbon or III-V compound semiconductor materials in the transistor channel provide a broad set of possibilities, one source of uncertainty is determining what 7nm or 5nm means in the context of the upcoming IC manufacturing nodes.

Prof. Asen Asenov of Glasgow University and CEO of Gold Standard Simulations.Prof. Asen Asenov of Glasgow University and CEO of Gold Standard Simulations.The three semiconductor manufacturing leaders--Intel, Samsung and TSMC--are ramping up 16/14nm FinFETs production and preparing to move to a 10nm node, but the FinFET may not make it to 7nm, says Professor Asen Asenov, CEO of Gold Standard Simulations Ltd. (Glasgow, Scotland). The firm provides software to simulate nanoscale CMOS devices. However, Asenov says that the node labelled 14nm has a 20nm channel length. The 10nm node is likely to be similarly oversized.

Lucian Shifren, principal engineer at ARM. Lucian Shifren, principal engineer at ARM. Lucian Shifren, principal engineer at ARM, tells Electronics360 that node naming has become somewhat arbitrary. "The nominal 10nm is going to be more like what 11nm was expected to be—and 7nm will be like 10nm," he says.

In the NWT, the gate is wrapped all the way around the conducting channel. Because of this, it can control the current flow better than bulk planar CMOS, FDSOI and FinFET transistors. It offers a steeper sub-threshold voltage slope and reduced leakage current. The drive current can be enhanced due to confinement induced band splitting. What's more, in a lateral configuration, multiple nanowires can be stacked vertically in the same die area to increase the drive current at the same pitch, says Asenov.

Vertical or Lateral?

But will the transistors be vertical or lateral?

Shifren says he is confident that lateral transistors will come next. "Vertical wires are more difficult to make than horizontal. There are methods for making horizontal wires even if they are not quite ready for prime time," he says.

However, the single largest factor that determines lateral NWTs first is likely to be the benefit of allowing a steady evolution of established EDA tools and methods.

"Going vertical would be a massive change for the EDA community," he says. "Although FinFETs is stuck in the third dimension, they are still effectively defined in 2 dimensions with quantization in terms of the number of fins included." Shifren says it is possible to see evolution of FinFETs into lateral nanowire transistors. "But going vertical changes everything and therefore it is probably a pipe-dream."

Perhaps the best known method of making lateral NWTs is by the repeated use of epitaxially grown layers. The detail will depend on whether silicon, silicon-germanium, or III-V compound semiconductors are used for the channel, says Asenov.

Shifren agrees that epitaxial growth of multiple layers of alternating silicon and silicon-germanium and subsequent use of selective etching to remove alternate layers leaving bridging wires is one method that can also be used with III-V heterostructures. Engineers can then use ALD (atomic layer deposition) to coat around the structure.

Curse of the Very Small

But there is still plenty of engineering to be done about optimum insulation and gate layers, and NWTS will not escape the "curse of the very small," says Asenov. "They will be as susceptible to local, statistical variability including such factors as random discrete dopants (RDD), gate edge roughness (GER), fin edge roughness (FER) and metal gate granularity (MGG)."

Ultimately, NWTs can scale to channel lengths of approximately 5nm—a point at which quantum tunnelling would disrupt conventional transistor operation. But choice of channel materials is critical, Asenov says. Understanding the operation and optimization of CMOS transistors at 7nm and beyond will be complex due to strong quantum mechanical effects and quasi-ballistic transport.

Aaron Thean, logic research director at IMEC.Aaron Thean, logic research director at IMEC.Aaron Thean, director of the logic research program at research institute IMEC, says that for some time gate length has not been the sole parameter that drives performance and circuit density.

"For the 14nm node, the gate pitch is about 70nm and for 10nm it is 54nm, 42nm. So scaling gate and contact pitch is what is driving us," he tells Electronics360. "With the FinFET, we got addicted to electrostatics. As you scale gate length, you need to squeeze the channel much harder.' As a result, he says that two trends can be identified: either slow down gate scaling so an architecture is not needed, or scale aggressively in which case a new architecture is needed.

Shifren agrees that contact resistance and device capacitance are now among the more pressing issues. He says that rather than the familiar march down the nodes, the semiconductor industry is going to see long-lived nominal nodes with a series of incremental changes as improvements are made.

"We've already seen the start of that with 16FF+," Shifren says, speaking of a second generation of FinFET from TSMC.

With or without EUV?

However, even for those who wish to move aggressively toward a nanowire transistor, it may be too late for the 7nm node.

"7nm circuits need to go into design next year (2016) for production in 2017," says Thean. As a result, 5nm is where most industry watchers expect to see nanowires coming in.

Can such aggressive adoption of 7nm node be achieved? "For 7nm it looks like the real gating factor is EUV," or extreme ultraviolet light, says Shifren. EUV is the long-awaited next-generation lithography that uses light of 13.5nm wavelength.

Thean is less sure that 7nm will depend so heavily on EUV. Given TSMC's stance on 7nm (see TSMC Aims for 7nm in 2017), perhaps immersion lithography alone can work. "EUV is definitely a cost reliever, but even EUV may have to be multi-patterned," says Thean. "EUV for 7/5nm nodes means you can print 2D patterns again."

For Thean, the lateral nanowire transistor is more likely the evolution from the FinFET. "There is a zoo of options around lateral and vertical NWTs but we target our research on the lateral NWT because it looks like a fin." He says that the vertical NWT forces a new architecture to be put in place. Beyond 5nm mode, atomic-level control of materials may force a change to a vertical process, he says.

What Material?

What material is going to be used in the nanowire transistor channel?

ARM's Shifren claims germanium-doped silicon is likely to be the way forward for reasons of evolution and continuity. He says that higher electron mobility materials—such as germanium, III-V compound semiconductors, and carbon in graphene or carbon nanotube forms—are misplaced in such nanometer structures because of short channel effects.

"Gate-all-around silicon is most likely for a 'real' 7nm," Shifren says. He adds that the nominal 7nm would likely be a pseudo-scaled FinFET and that the nominal 5nm process would be gate-all-around.

Thean agrees, "At IMEC we look at silicon, silicon-germanium and III-V channel materials but the preference is silicon." Other materials suffer from immaturity. "You have to ask what is the value proposition for these materials? SiGe improves mobility but there are issues of reliability. It is very difficult to passivate the surface." So for Thean, at least, progress is likely to be based in silicon with first-scaled FinFET. That means a taller fin, then movement to lateral nanowire transistors. But it still needs some level of innovation, he says.

Thean says that outlook means that foundries and IDMs may not converge on the same device architecture, which could drive up cost. Time to market is likely to be key. "How soon can a company master and introduce any innovation," he says.

Speed of introduction is where Professor Asenov reckons companies like his can help. "The GSS TCAD tool chain can significantly reduce the cost and risk associated with making the right decisions when moving to NWT CMOS technology," he says. "It can also help fabless companies make the right technology choices for their products in the diversified-technology world where NWT technology will compete with conventional bulk, FDSOI and FinFET CMOS."

Asenov says, "I do not think that there is a real alternative to NWTs. They are a natural progression to FinFETs. Think of it like this: MOSFET—gate on the side of the channel; FinFET—gate on three sides of the channel; NWT or gate all around—gate on four sides of the channel." In a word, ultimate control of the current.

Questions or comments on this story? Contact peter.clarke@ihs.com

Related links and articles:

www.arm.com

www.imec.be

www.goldstandardsimulations.com

IHS Technology Semiconductors and Components Page

News articles:

TSMC Aims for 7nm in 2017

IBM Integrates III-V Nanowires on Silicon

Xilinx, TSMC Team for 7nm Process Technology

IMEC Builds Compound FinFETs on Silicon

IMEC Boosts Directed Self-assembly Lithography Process

TSMC Tweaks 16nm FinFET to Match Intel



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