Intellectual property (IP) firm Menta SAS has introduced its third generation of embedded field programmable gate array (eFPGA) technology for system-on-chip (SoC) designs.
Menta says the eFPGA technology will provide a 20% boost in power performance over the previous generation of IP. Based on the company’s Origami tool chains, the eFPGA technology includes synthesis to allow register-transfer level (RTL) applications in VHDL, Verilog or SystemVerilog as well as new SDC support for application design constraints.
The third generation of IP technology includes a new embedded logic block design with a look-up table (LUT), which can be configured into a variety of LUT-based configuration, combinational functions such as full adder, comparator, equality, multiplexer and ROM. The IP also offers full testability to allow fault coverage up to 99.8% and support for Taiwan Semiconductor Manufacturing Corp. (TSMC) 28nm manufacturing node.
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