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Electronic Design Automation

Cadence Receives Certification for TSMC’s 16nm FinFET Process

15 June 2015

Cadence Design Systems Inc. has received certification from Taiwan Semiconductor Manufacturing Corp. (TSMC) for its 16 nanometer (nm) FinFET Plus process.

The two companies are also collaborating on the certification process to port Cadence’s (San Jose, Calif.) Innovus implementation system to TSMC’s 10nm FinFET process with a target for completion set for later this month. The announcement was made during the 2015 Design Automation Conference (DAC) held in San Francisco.

The Innovus tool enables system-on-chip (SoC) developers to deliver designs with a higher level of power, performance and area (PPA) while also accelerating time-to-market, Cadence says. The certification of TSMC’s Innovus system includes GigaPlace placement technology for electrical and physical design closure, integration with Cadence Quantus extraction solution, its Tempus timing signoff solution, Voltus IC power integrity solution and Cadence’s Physical verification system.

Also at DAC, Synopsys Inc. rolled out a portfolio of intellectual property (IP) for SoC automotive designs. Synopsys’ DesignWare IP includes an Ethernet audio video bridging (AVB), LPDDR4, MIPI CSI-2 and DSI, HDMI, PCI Express, USB, mobile storage, logic libraries, embedded memories, nonvolatile memories, data converters, ARC EM processors, EV vision processors and sensor and control IP libraries.

Use of these cores helps customers to meet automotive functional safety requirements and allows for the acceleration of safety assessments in applications such as advanced driver assistance systems (ADAS) and infotainment.

TSMC also announced it is collaborating with Imagination Technologies to develop new intellectual property (IP) subsystems for the Internet of Things (IoT) in order to simplify designing products in this space.

The IP platforms work with reference design flows on TSMC’s process technologies from 55nm down to 10nm. The IP IoT subsystems include small, highly-integrated connected cores for simple sensors, which combine entry-level M-calls MIPS CPU with an ultra-low power Ensigma Whisper RPU for Wi-Fi, Bluetooth Smart and 6LowPan.

The collaboration is targeted at SoCs for a wide range of IoT applications including smart surveillance, retail analytics and autonomous vehicles.

Questions or comments on this story? Contact dylan.mcgrath@ihs.com

Related links:

www.cadence.com

www.tsmc.com

IHS Semiconductors & Components

News articles:

To contact the author of this article, email Peter.Brown@ieeeglobalspec.com


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