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Semiconductors and Components

Globalfoundries, Intel Roll Out Support for 14nm Design

05 June 2015

Globalfoundries Inc. (Santa Clara, Calif.) announced it can supply physical design kits (PDKs) and access to standard cell libraries for customers to design on its 14-nanometer (nm) FinFET manufacturing process. Meanwhile Intel has certified that Synopsys' Galaxy design platform is good for designing to its 14nm FinFET process.

Intel has been running the 14nm FinFET process for several quarters for its own chips. Intel also has some customers for whom it also manufactures devices on the process.

As for Globalfoundries, it is already running the 14nm process and is on schedule to support multiple product tape-outs and volume ramp in 2015, suggesting that its lead customers are already well advanced with their chip designs.

A FinFET-based manufacturing process with transistors contained in fins that rise up from the IC surface is more complex than the planar bulk CMOS at 28nm or 20nm, putting further demands on designers and design support.

The design flows worked out by Globalfoundries go from the register transfer level, which represents the end-point of high-level design, down to GDS, a graphical description that can be used as the starting point for files to drive manufacturing equipment such as lithography.

Working with the three leading EDA software and circuit block suppliers—Cadence Design Systems Inc., Mentor Graphics Corp. and Synopsys Inc.—Globalfoundries has prepared starter kits that include features to address 14nm challenges.

These include: implant-aware placement, double-patterning aware routing, local/random variability aware timing, 3D-aware parameter extraction for FinFETs and in-design design rule checking (DRC) for iterative yield improvement, the company says in a statement. The digital design “starter kit” provides designers with a built-in test case for physical implementation, testing and analysis of performance, power and area.

Multiple tools from Cadence and Synopsys have been extended to cope with the 14nm process and can take designs through design entry, synthesis, design validation, parasitic extraction and timing sign-off. As with production tape-outs at prior nodes, the starter kit uses the Mentor Graphics Calibre tool suite for sign-off. The Calibre nmDRC and Calibre MultiPatterning products are used for layer decomposition, DRC verification and metal filling, while the Calibre nmLVS product is used for logic verification.

However, this is not Globalfoundries' first FinFET process. The foundry spent time and money developing its own 14nm FinFET process and even planned to start multiproject wafer (MPW) in 2014. However, the appointment of CEO Sanjay Jha to replace Ajit Manocha at the beginning of 2014 brought with it a change of strategy and an agreement to form a 14nm alliance with Samsung based on Samsung's 14nm FinFET process (see Samsung, Globalfoundries Form 14nm Alliance to Fight TSMC).

This was largely driven by the desire of a few key customers, including Qualcomm and others, to have access to multiple foundries for the manufacture of their leading edge SoCs after TSMC had achieved a near monopoly position in the supply of 28nm wafers in 2012.

A risk to Globalfoundries was that, as a junior partner to Samsung on 14nm FinFET it might be seen not only as second source but also as a second-class option that would be late with availability, options and improvements.

"Globalfoundries is committed to providing our customers with advanced technology platforms that include the comprehensive design infrastructure required to optimize design productivity and cycle time," says Rick Mahoney, senior vice president of design enablement at Globalfoundries, in a statement.

Meanwhile Intel Custom Foundry is also offering a system-on-chip (SoC) design flow for 14nm implementation and sign-off based on the Galaxy design platform. Synopsys and Intel used a PowerVR Series6 GPU from Imagination, together with DesignWare memory compilers as the certification vehicle to validate the RTL- — to — GDSII methodology.

"We have certified the Synopsys Galaxy Design Platform for our mutual customers to implement, verify and signoff differentiated SoC designs targeting Intel's 14nm technology with our second-generation of tri-gate transistors in high-volume manufacturing," said Ali Farhang, vice president of design enablement at Intel Custom Foundry, in a statement issued by Synopsys. "This certification was only possible through a collaborative three-way effort by Intel Custom Foundry, Synopsys and Imagination Technologies."

The Synopsys Galaxy Design Platform is available for both the 22nm and 14nm FinFET processes at Intel. DesignWare Memory Compilers and DDR3/2 PHYs are also available today.

Questions or comments on this story? Contact peter.clarke@globalspec.com

Related links and articles:

www.globalfoundries.com

www.intel.com/foundry

IHS Technology Semiconductors and Components Page

News articles:



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