EDA vendor Mentor Graphics Corp. has rolled out a software package that works with its Veloce emulation platform to enable a new methodology for power analysis of complex system-on-chip (SoC) designs at the system, RTL and gate level.
Mentor maintains that current methods for SoC power analysis are inadequate for today’s complex SoCs, many of which are used in handheld and smart consumer electronics devices. Often, the power analysis done on these devices does not properly account for real-world use cases, Mentor says.
Current power analysis methods rely on an adapted functional test bench. But this test bench does not capture operating system boot up or applications activity, according to Mentor.
Complex SoC designs are now verified using live applications that require booting the operating system and running software applications on an emulator, Mentor says. The company says that it is more effective to use the power switching activity plot generated during emulation to pass real-time switching activity information to power analysis tools so that potential power issues can be evaluated.
The Veloce Power Application is “a new way of analyzing the power consumption of a chip,” says Jean-Marie Brunet, a marketing director at Mentor. Using the test bench method is no longer effective for today’s complex SoCs, he says.
Longtime EDA analyst Gary Smith, founder and chief analyst at Gary Smith EDA, says the International Technology Roadmap for Semiconductors (ITRS) has for several years emphasized issues related to dynamic power. “A new approach to the transfer of power switching activity data captured during emulation is the right direction for the industry,” Smith says.
The Veloce Power Application replaces the file-based power analysis flow with a Dynamic Read Waveform API integration to power analysis tools. This approach captures the information from the power switching activity plot and transfers that data to power analysis tools, Mentor says. Ultimately, it enables accurate power calculation at the system level, better power exploration at RTL for power budgeting and tradeoffs and more accurate power analysis and sign-off at the gate level, according to Mentor.
The result, Mentor says, is a boost in both runtime and performance. The company says that customers who have had early access to this technology have reported up to a 4.5X runtime performance improvement.
The traditional knock on emulation has been the cost of the emulation system, which can be several million dollars. But Brunet says this is less of an obstacle today than it was several years ago, because customers realize that accurate simulation of today’s complex SoCs simply takes too long. The cost to chip companies of not finding issues prior to design tape out can be devastating, he says.
“The way we see it is, how much does it cost to find two or three bugs in silicon? Usually, the response to this is often several orders of magnitude higher [than the cost of an emulation system],” Brunet says.
As part of creating the Veloce Power Application suite, Mentor took the unusual step of partnering with a rival EDA vendor, Ansys. That company is the first Veloce Power Application ecosystem partner with its PowerArtist power analysis tool.
Brunet says most of Mentor’s customers indicated that they were using PowerArtist for power analysis signoff, prompting the company to partner with Ansys. “We had to do what customers were telling us to do,” he says.
The Veloce Power Application integration with Ansys PowerArtist is available to mutual customers on a limited basis, Mentor says. The full production release is scheduled for early in the fourth quarter. Pricing information was not disclosed.
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