The DDR3 IP is the result of a year-long project to coordinate the subsystem IP into Samsung’s 28nm LPP process. The project results were better than expected, improving memory performance by more than 10%, Uniquify says.
The DDR3 IP is currently being used in Samsung’s foundry production lines for both consumer and mobile applications.
The DDR PHY IP counteracts the effects of timing shifts due to both static and dynamic variation caused by process, temperature and voltage. Timing shifts happen when the system-on-chip and DDR memory become misaligned. Even at the picosecond level, that could result in a subsystem or even an entire system failure.
Using both dynamic self-calibrating logic (DSCL) and dynamic adaptive bit calibration (DABC), the DDR PHY IP allows the DDR memory interface to be optimized for speed at a low power and high performance, Uniquify says.
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