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Electronic Design Automation

Cadence Tools Certified for TSMC’s 10nm FinFET Process

06 April 2015

EDA vendor Cadence Design Systems Inc. says its digital and custom/analog design tools have achieved certification for Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC)’s current 10nm FinFET design rule manual and Spice models.

Cadence (San Jose, Calif.) says its custom/analog and digital implementation and signoff tools have been certified by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure on the 10nm FinFET process.

Cadence tools certified by TSMC for the 10nm FinFET process include: Encounter Digital Implementation Syste, Innovus Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Quantus QRC Extraction Solution, Virtuoso Custom IC advanced-node platform, Spectre simulation platform, Physical Verification System, Litho Electrical Analyzer.

TSMC’s 10nm libraries are also created using the Cadence Virtuoso Liberate Characterization Solution and Spectre Circuit Simulator, Cadence says.

"The certification of Cadence custom/analog and digital implementation and signoff tools ensures design solution readiness for customers to achieve reduced iterations and improved predictability with 10nm FinFET designs,” says Suk Lee, senior director for TSMC’s design infrastructure marketing division, in a statement.

Questions or comments on this story? Contact dylan.mcgrath@globalspec.com


Related links:

http://www.cadence.com/

IHS Technology Semiconductors & Components Page

News articles:



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