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Processors

Xilinx Tips 16nm FinFET FPGAs

24 February 2015

Xilinx Inc. has announced that its UltraScale+ family of FPGAs, 3D chips and MPSoCs will be implemented in the 16FF+ FinFET process being developed by foundry Taiwan Semiconductor Manufacturing Co. Ltd. First shipments are expected before the end of 2015.

At the high-end, the multiprocessor system on chips (MPSoCs) will include multiple ARM cores. Overall, the 16nm FinFET devices will achieve between a factor of two and a factor of five greater system-level performance per watt than devices implemented in 28nm CMOS, Xilinx said. First tape outs are expected in the second quarter of 2015 and shipments are forecast for the fourth quarter of 2015.

The UltraScale+ portfolio comprises Kintex FPGAs; Virtex FPGAs and multi-die components making use of 3D packaging; and the Zynq family of multiprocessor system-on-chip (MPSoC) ICs. Xilinx said it is aiming to address applications in 5G wireless, terabit per second wired communications, automotive driver assistance systems (ADAS) and industrial Internet of Things (IoT).with the portfolio.

Zynq MPSoCs will include a 64-bit quad-core Cortex-A53 processor capable of hardware virtualization and supporting ARM TrustZone technology. Alongside this will be a dual-core Cortex-R5, which is optimized for deterministic operation, high throughput and low latency. A separate security unit enables military-class security solutions such as secure boot, key and vault management, and anti-tamper capabilities—standard requirements for machine-to-machine communication and industrial IoT applications.

The Zynq MPSoC will include graphics rendering courtesy of a Mali-400 GPU and a video codec for H.265 video compression and decompression, combined with support for Displayport, MIPI and HDMI. Finally, a dedicated power management unit (PMU) has been added to support system monitoring, system management, and dynamic power gating for each of the processing engines.

The UltraScale+ devices will also include up to 432Mbits of SRAM on-chip in a variety of configurations for use in applications such as deep packet and video buffering.

The family will also include an innovation in connection technology called SmartConnect. Xilinx claims that the use of interconnect optimizations designed to match application-specific throughput and latency requirements can provide an additional 20 to 30 percent improvement in performance, area and power consumption compared with FPGAs without the SmartConnect technology.

Questions or comments on this story? Contact: peter.clarke@globalspec.com

Related links and articles:

www.xilinx.com

IHS MCU and MPU research

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