Achronix Semiconductor Corp. has announced that it has reached volume production for its Speedster22i family of FPGAs and is preparing to offer higher levels of integration as will as planning a move to 14nm FinFET production. Achronix FPGAs include larges amounts of hard IP to customize them for high-bandwidth, high-performance applications in wireline communications.
Although Achronix (Santa Clara, Calif.) has been two years getting to volume production status it does imply the company has solid revenue coming in and that its fate could be different to rival FPGA company and near neighbor Tabula Inc. Tabula is reportedly closing its doors in March 2015.
The Achronix Speedster22i family was originally announced in April 2012 with a view to sampling devices later that year. During the long gestation period the company has also trimmed down its HD series of Speedster22i parts to three devices and made no mention of the previously announced HP series. The two devices that have entered volume production are the the HD680 with 660,000 effective look-up-tables (LUTs) and the HD1000 with 1 million effective LUTs.
The HD1000 has two 100 Gigabit Ethernet controllers, two 120 gigabit Interlaken controllers, two PCIe Gen3 x8 controllers and six 1866 Mbps DDR3 controllers – equivalent to 350,000 LUTs of logic that is eliminated from being implemented in the programmable fabric. In addition to freeing up the programmable fabric, the hardened IP also speeds up development time because the IP meets timing and does not need to be placed and routed. The HD1000 also has 86 Mbit of on-chip RAM, 64 high performance SerDes lanes and almost a thousand programmable I/O.
Steve Mensor, vice president of marketing at Achronix, told Electronics360 that the company had started sampling Speedster22i parts in March 2013 and went into volume production at the end of 2014. Mensor said there had been no problems with the availability of the Intel 22nm FinFET process but that verifiying the large amount of hardened IP that it chosen to include in its FPGAs had presented challenges to a small company. Mensor declined to say whether Achronix had required a major respin of the FinFET silicon but said: "Getting all this IP up and working reliably did take time. The good news is we worked with customers on their design-in cycles and all their device qualifications are complete."
Concerning the dropping of the HD210 device with 260,000 LUTs, Mensor said: “It was targeted at a lower cost point that ultimately did not make sense.” Mensor added: “We were not able to get the HD1500 out yet, but we’re OK with the two devices.” He declined to discuss the higher performance HP360 and HP560 that had previously been listed in the Speedster22i family.
Hard IP helps design closure
The Speedster22i family is supported by the Achronix CAD Environment (ACE) tool suite, which includes Synplify Pro for Achronix from Synopsys. Achronix also has development boards and a range of reference designs.
"Developing high-end FPGAs with up to six billion transistors is complex and challenging,” said Mensor, in a statement. "Achronix FPGAs with hard IP targeted for high performance wireline applications that are now in production offer a lower power and lower priced solution than the alternative general purpose FPGAs from other vendors."
Mensor stressed that the development environment for the Speedster22i family was finding favor among customers because allowed timing closure much more readily than working with a general-purpose FPGA. "They can do this with Altera or Xilinx but they find it difficult to implement without direct support."
"We are working with strategic customers on more integrated devices that will be added to the portfolio in the next six months," said Mensor. He declined to provide further detail except to say that the devices would have extra hard IP but pursuing similar high-bandwith, high performance applications. "Adding IP will make the devices narrower, less general purpose, but these could be some high volume sockets," he said.
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