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Semiconductors and Components

Cadence Rolls IP Processors

12 January 2015

Cadence Design Systems Inc. has rolled out the 11th generation of its Tensilica Xtensa processors offering up to 75 percent better local memory area and power efficiency.

With up to 25 percent less processor logic power consumption, the Xtensa 11 processor intellectual property includes enhancements to flexible length instruction extensions (FLIX) allowing for very long instruction word (VLIW) instructions of any length from 4 to 16 bytes. This allows for 25 percent less power compared to prior Xtensa generations, Cadence said.

Other architectural improvements to the IP processors include an option to run-time power-down of cache memories that leads to 75 percent local memory power savings in select operating scenarios Cadence said. The Xtensa 11 also provides more efficient data cache block that lowers system power and boosts system performance by speeding functions such as MemCpy by 6.5 times faster and reducing the total number of system bus read operations by up to 23 percent, the company said.

Jack Guedj, corporate VP of Tensilica products at Cadence, said in a statement the Xtensa 11 allows customers to “create fully optimized processors for many applications” that can be done in record time and with Cadence’s latest development tools.

Questions or comments on this story? Contact dylan.mcgrath@ihs.com

Related links:

www.cadence.com

IHS Semiconductors & Components

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Cadence Expands EDA Software Suite for FPGA Prototyping

Synopsys to Provide Tools for Chinese FPGA Startup



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