Synopsys Inc. has expanded its agreement with nanoelectronics research center Imec to include nanowire, FinFETs, Tunnel-FETs and other devices targeting the 5nm technology node and beyond.
The expansion of the collaboration will Synopsys to provide process-calibrated models for its Sentaurus technology computer aided design (TCAD) tools to chip makers developing 5nm products. The two have already completed implementations of the technology tools on FinFET and 3D-IC technologies for 10nm and 7nm technology nodes.
An Steegen, senior VPO of process technologies at Imec, said in a statement the collaboration will allow the companies to “tackle the physics and engineering of advanced devices” as well as to help “introduce a new device design infrastructure for the industry.”
The TCAD tools that Synopsys uses in this agreement include its Sentaurus Process, Santaurus Device, Sentaurus Interconnect and Raphael. As part of the agreement, the duo is investigating a vertical nanowire-nanosheet hybrid SRAM cell to target 5nm technology and other topics. These other topics include fundamental device physics, middle-of-line (MOL) local interconnects and the optimization of parasitics. One important part of the collaboration will involve full-3D process and electrical simulations to identify device and interconnect reliability offerings for scaled circuits, Synopsys said.
Anda Mocuta, logic device manager at Imec, said in the same statement that the expansion of the agreement is the first time a process-calibrated TCAD simulation flow has been used “to comprehensively study the process, device and circuit architectures” that is early in the path-finding technology process.
Synopsys said Imec’s technology prototyping and characterization capabilities are a good fit to bring advanced Sentaurus TCAD models to address challenges developers are facing at the 5nm node level.