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Cadence CTO Rowen Forecasts Processor Design Split

22 September 2014

Chris Rowen, CTO of the IP Group at Cadence Design Systems Inc. (San Jose, Calif.), has developed a vision of how system-on-chip architecture is evolving in the era of the Internet of Things and has concluded that processor architectures will become more diverse and their design style will bifurcate into least two major categories. Rowen added that this vision is driving future product development at Cadence.

One example is that neural network processor architecture is being worked on at Cadence as part of research into how much diversity is required to serve the market, Rowan said. However, he added that there at present no plans or timetable for the introduction of a configurable neural network processor IP block.

Chris Rowen, CTO of the IP group at EDA firm Cadence.

Rowen, who came to Cadence as the founder of Tensilica Inc. with an acquisition in 2013 and had previously worked at MIPS, laid out his vision in a presentation to journalists at a multi-company meeting held in Tegernsee, near Munich, Germany, last week. He said that the evolution and bifurcation of processor architecture is being driven by a dramatic increase in data capture and transmission and by the corresponding need to drive down energy consumption to support that.

One branch is represented by the extension of the traditional general-purpose processors, optimized for performance, that benefit from leading-edge manufacturing processes. The second branch will be diverse, application-specific with tailored data types and a focus on low-energy. It is this second design style that will be best suited to the upcoming markets in wearable equipment, smart-home, medical and industrial IoT, Rowen said.

Rowen said the first branch as being analogous to mammals in the animal kingdom – complex, adaptable but power hungry. Rowan compared the second category to extreme diversity of insects that are highly focused on their niche and power efficient. He noted that there are only about 4,000 mammal species in the animal kingdom but there maybe as many as 4 million insect species.

The processor world will divide into 'mammals' and 'insects' Source: Chris Rowen, Cadence.

The dramatic increase in data that would result from the proliferation of the use of sensors means there is a need to "do as much processing locally as is possible. The need for low-energy is driving a model of layered cognition," Rowen said.

He illustrated this with the example of a speech recognition application that is performed initially on a mobile device and only goes out to the cloud infrastructure as the processing load increases. "I think microphones and image sensors are among the most significant sensors because they not only generate the most data but also have the most scope to change the human-machine interface," Rowen said.

Layered cognition allows processing to be done at the most local place possible. Source: Chris Rowen, Cadence.

The IoT label doesn't do justice to the diversity of tasks, he said predicting that while IoT may be the "Word of the Year for 2014 it will be replaced by specific words for various sectors as volume markets for silicon emerge: wearables, smart-home, industrial, automotive and medical.

Rowen said the choice and support of appropriare algorithms and datatypes was the key to producing energy efficient designs of processors and so would drive instruction set optimization, interconnect alternatives and alternative memory partitions. He characterized as an exponential continuation of the work Tensilica has already been doing with DSP variants but supported now Tensilica owned by Cadence by layout and analysis tools.

"Tensilica has delivered 6,000 IP variants including 2,300 DSP variants and now has over 3 billion cores deployed," said Rowen. "'Insects' will push Moore's Law much less fiercely and make use of the 28nm node and above. 'Mammals' will benefit from 16nm FinFET and beyond," Rowen concluded.

When asked where sub- or near-threshold voltage operation fitted in to this vision Rowen said that some applications could benefit from sub-threshold but that they would be few and far between because the performance characteristics of sub-threshold are not very attractive. "The real action is between nominal voltage and 120 percent of threshold. Even there the ecosystem is not very good." He added that this showed how the tools for "insect" design were key enablers of specialization.

Similarly with regard to reduced data resolution and neural networks, he said. However, with deep digital neural networks Rowen postulated that these could be hosted on digital processors, despite an implicit loss of efficiency. "Can it sit on top of a DSP? Digital neural networks look like a lot of other processors. Where is the time spent in a convolutional neural network? In convolution which may be amenable to instruction set optimization," he said.

When asked if Cadence was working on neural networking as an IP approach Rowen said: "It's one of the things we are working on

Related links and articles:

www.cadence.com

IHS semiconductor value chain research

News articles:

IBM Seeks Customers For Neural Network Breakthrough

Startup Preps Neural Network Visual Processor for Mobiles

Intel Follows Qualcomm Down Neural Network Path

Qualcomm Working on Neural Processor Core

Startup Seeks Funds to Realize 'Belt' Processor

Micron Preps Memory-Based Automata Processor



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