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Tunnel FETs to Save Power by 2017, Says Toshiba

11 September 2014

Toshiba Corp. is moving forward on the idea of the tunneling field effect transistor (TFET) as a means of cutting power consumption in complex ICs such as microcontrollers by a factor of ten. The company has said it plans to integrate TFETs with conventional CMOS in microcontroller targeting commercial production and use by 2017.

Researchers from Toshiba presented three papers at the 2014 Solid State Devices and Materials (SSDM) in Tsukuba, Japan on Sept. 9 and 10. Two presentations were based on joint research with the Collaborative Research Team Green Nanoelectronics Center (GNC) at the National Institute of Advanced Industrial Science and Technology (AIST).

And Toshiba is not alone in seeing the TFET as a way forward. For the same conference researchers from Intel prepared an invited paper Tunnel-FET Transistors for 13nm Gate-Length and Beyond. This illustrates the role of the Tunnel FET and or the junctionless transistor as the next transistor type to come after the FinFET runs out of steam or as its refinement.

Toshiba's claim that a novel transistor type could be developed, fully characterized and embedded in CMOS for commercial production within three years is extremely ambitious.

TFETs switch by modulating interband quantum tunnelling through a barrier rather than thermionic emission over a barrier as in traditional MOSFETs. One results of this is that TFETs can have a much sharper subthreshold voltage swing than the 60mV/decade at room temperature of conventional MOSFETs.

Toshiba believes the TFET operating voltage can be reduced to lower than half that of the MOSFET, specifically lower than 0.5V, and the off-state leakage current of TFET might be reduced to about 1 percent of the MOSFET, a Nikkei article reported.

While numerous TFET device types have been reported they have mainly been in more exotic III-V material systems and Toshiba's breakthrough has been to produce two different devices in silicon that are CMOS-compatible, one optimized for logic and the other for SRAM. The company is proposing that by applying each TFET into some circuit blocks, it is possible to achieve significant power reductions in MCUs.

The logic TFET has ultra-low leakage current while the SRAM TFET has low variation in transistor characteristics and both utilize vertical tunneling to enhance the tunneling properties, Toshiba said. In addition, the logic TFET employs precisely controlled epitaxial material growth process for tunnel junction formation with carbon and phosphorus doped Si.

For the SRAM-type TFET development, Toshiba has proposed a TFET operation architecture that doesn’t need to form a structural tunnel junction and therefore reduces transistor characteristic variability.

Related links and articles:

www.semicon.toshiba.co.jp

www.ssdm.jp

IHS MCUs and MPUs research

News articles:

Startup Claims Quantum FinFET is World Beater

Synopsys' de Geus: FinFET Transition Gaining Momentum

Fins Ain't What They Used To Be

TSMC to Fall Behind Rivals in FinFET Market Share



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