Imagination Technologies Group plc (Kings Langley, England) has announced another member of its MIPS Warrior family of processor cores, the 64-bit I6400, which is intended to address a mid-tier of applications from embedded equipment through mobile devices and digital consumer electronics up to networking and storage.
As such the architecture is being pitched against the 64-bit capable Cortex-A5X series from ARM Holdings plc (Cambridge, England), which is licensed by scores of chip companies and is gaining design wins in a applications form smartphones and tablet computers up to servers.
Imagination is claiming that the I6400 core has superior computing efficiency and performance to the competition as well as such features as multi-threading and a clustering fabric to support scalable coherency.
Imagination's MIPS Warrior cores come in three classes – M, I and P – and the company cited a similar list of application targets for its first Warrior class core, the P5600 launched in October 2013 (see Imagination Fights Back with Warrior MIPS Core). But the P5600 has yet to be seen in many design wins and only offered 32-bit capability while many markets, mobile in particular, have been moving quickly to 64-bit.
MIPS Series 6
Imagination claims that I6400 has taken a performance/power/area leadership place that is "far ahead of the competition." The I6400 core has a 50 percent higher CoreMark performance and 30 percent higher DMIPS compared the best of the competitors "in its class." However, the main differentiation from ARM would appear to be hardware support for multithreading – up to four threads per core – and support for clustering to help scale I6400 systems up to 100s of cores.
Meanwhile there is no explicit help for big-little type architectures where cores optimized for different work loads can be used at different times during a system's wake-idle-sleep life cycle. However, licensees can use something called PowerGearing to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
Scalability via clustering is supported by the MIPS Coherency Manager Fabric based on a new coherent interconnect architecture. It supports multicore configurations of up to six cores per cluster where multiple cores on a single cluster can have different synthesis targets, and operate at different clock frequencies and voltages. The Coherency Manager fabric implements numerous high-performance features including hardware pre-fetching as well as wider buses and lower latencies compared to previous generations. I6400 cores are designed to be delivered in diverse combinations of threads, cores and clusters, supporting multi-cluster fabric configurations up to 64 clusters. The cores are also designed to operate in heterogeneous clusters in future SoC implementations leveraging CPUs, GPUs and other processing elements.
MIPS I6400 block diagram. Source: Imagination
"As the industry moves toward instruction set neutrality, customers can now choose a CPU based on its technical superiority. The I6400 is more efficient, flexible and scalable than the competition, and its feature set clearly lends itself to the needs of a wide range of next-generation applications including smartphones and tablets," said Tony King-Smith, executive vice president of marketing at Imagination, in a statement. "We know that unique features like multi-threading provide significant advantages for many applications, and customers already using this technology agree. Unsurprisingly, we've already secured licensees for the I6400 across multiple markets."
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