Intel has just given some of the first details of its 14nm FinFET manufacturing process and the benefits it will deliver to mobile processors (see Intel Presents Broadwell CPU, 14nm FinFET Process).
As is the Intel way only few little bits of information are released at a time so that the company can return to the marketing well multiple times. It's a bit like being given a few bits of a jigsaw puzzle at a time to try and maintain interest.
However, despite the gradual and piece-meal disclosure at least one observer appears content that Intel's second generation FinFET puts right some things that hindered the performance of the first generation.
When Intel's 22nm FinFET was introduced in 2012 it was technically the most advanced chip manufacturing process available but it was a disappointment to many observers because it failed to deliver the anticipated reduction in power consumption compared with 32nm planar CMOS.
At the time Professor Ase Asenov, founder and CEO of TCAD company Gold Standard Simulation Ltd. (Glasgow, Scotland) pointed out that the slope-sided trapezoidal cross-section of the Intel 22nm FinFETs is sub-optimal resulting in stronger short-channel effects and up to a 15 percent reduction in current compared to an "ideal" rectangular FinFET.
GSS publicized TCAD simulations based on the Intel structures mainly, of course, to show of the capabilities of its Garand atomistic 3D TCAD simulator.
Slope-sided versus rectangular fins
At the time it was argued that the slope-sided fins were a means of reducing complexity in manufacturing and therefore helping the 22nm chips to achieve the yields necessary for production. The counter argument was that the physical and electrical variability of these trapezoidal fins required disciplined design away from corner cases and more or less killed off the expected advantage of moving away from planar CMOS. Certainly Intel processors in 22nm FinFET were not deemed by the market to be suitable for mobile and battery-operated equipment.
GSS has now looked at Intel's second-generation "rectangular" 14nm FinFET structure and fortuitously has recently published a paper detailing a simulation of a similar structure. However, it should be noted that as geometries decrease the fins, while they may become qualitatively rectangular depart from the ideal shape plugged into the GSS simulator to an even greater extent.
Are those 14nm fins rectangular? Source: Intel.
"From first glance the reduced fin pitch and increased fin height suggest more than 1.7x improvement of the drive current," said GSS in a blog entry that is uncredited to any author (see Has Intel Learned from GSS Predictive Simulations?). This could be consistent with Intel's argument that it only needs two fins per transistor at 14nm rather than three fins per transistor at 22nm, although contact resistance and compressive strain will both impact the drive current.
Intel's fins are reported to be 42nm tall on a 42nm pitch and with a gate pitch of 70nm. GSS has simulated a similar rectangular-shaped FinFET with a 44nm tall fin and 40nm pitch. The simulated gate pitch is 64nm.
According to the simulation the intrinsic pFinFET drive current of the transistors in the paper can be more than 1.6mA/micron with a supply voltage Vdd of 0.75V. This is based on the assumption that 1.5GP of compressive strain can be introduced into the channel by suitable source/drain engineering.
GSS has supplied foundry chip maker with its TCAD software for some time and announced in July 2014 that it had licensed its complete TCAD/EDA software suite to Globalfoundries Inc.
The "multi-million dollar" deal includes Garand simulator, a compact model extractor and RandomSpice, the GSS statistical circuit simulator. The GSS software suite allows design and technology optimization that includes statistical variability and covers the three principle manufacturing styles, planar bulk, FinFET and FDSOI.
"The GSS simulation tools offer significant competitive TCAD advantages that support technology development by providing a seamless flow from Monte Carlo transistor simulation through physical simulation of statistical variability, extraction of accurate statistical compact models, and circuit simulation,” said Francis Benistant, TCAD manager at GlobalFoundries, in a statement issued by GSS.
Related links and articles:
Predictive Simulation and Benchmarking of Si and Ge PMOS FinFETs for Future CMOS, IEEE Transactions on Electron Devices, Vol. 61, No.7, pp2271-2277 (2014) L. Shifren, R. Aitken, A. Brown, V. Chandra, B. Cheng, C. Riddet, A. Alexander, B. Cline, C. Millar, S. Sinha, G. Yeric, A. Asenov,