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Cadence Expands EDA Software Suite for FPGA Prototyping

17 July 2014

Cadence Design Systems Inc. unveiled an expansion to its System Development Suite with the addition of Protium, the company’s proprietary rapid prototyping platform, for field programmable gate array (FPGA) software improvement.

The expansion of the development suite will support improved software development productivity and IEEE 1801 low power support in Cadence Palladium XP II verification computing platform. Cadence said these expansions will help system and semiconductor companies in the mobile, consumer, networking and storage markets address new design challenges such as early software bring-up and reduced power consumption.

Cadence claims the additions to its software will enable bring-up time by as up as 70 percent, shortening the process from months to weeks. The addition of the Protium upgrade not only supports the Palladium but features a 4x increase in capacity versus and support for up to 100 million gates. These features allow for a fully automatic flow and the capability to execute user-driven performance optimizations, the San Jose, CA-based company said.

Time to market is also accelerated due to automated memory compilation, external bulk memory support and RTL name preservation throughout the flow – reducing tedious and error-prone manual FPGA bring-up steps.

"The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping, allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks compared to traditional FPGA-based prototyping approaches," said Hideya Sato, deputy executive general manager, Global MONOZUKURI Division, Information & Telecommunication Systems Company, Hitachi, LTD, in a statement.

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