An STMicroelectronics research team has presented research results for the use of hafnium oxide as a non-volatile embedded memory. A presentation by Philippe Candelier, a memory researcher for STMicroelectronics NV at Crolles given at the Leti one-day memory workshop on June 24, gave results for a 16-kbit OxRAM test chip implemented in 28nm high-k metal gate process.
At the same meeting Jean-Michel Portal of the Institut Matériaux Microélectronique Nanosciences de Provence (IM2NP), who is working with STMicroelectronics in the French government backed DIPMEM project, outlined the direction the overall research is headed and said that a said that a "normally off" MCU tape-out was expected by the end of 2014.
The overall goal of DIPMEM is the development of magnetic RAM and resistive RAM embedded memory options for the 28nm fully-depleted silicon-on-insulator (FDSOI) manufacturing process and subsequent generations. The DIPMEM delivery vehicle is a normally off MCU implemented in 28nm FDSOI with non-volatile memory throughout, as well as conventional SRAM for higher performance operation when energy-efficiency is not essential.
However, for that ultra-low power MCU to be practical further improvements are required in the OxRAM technology according to the Candelier's presentation. It is notable that Panasonic has been supplying an 8-bit microcontroller with tantalum oxide based ReRAM as its internal memory since 2012 (see Embedded ReRAM Gets Into Distribution).
Candelier reported ST's chosen ReRAM structure is a bipolar resistive stack with 5nm layer of HfO2 between the TiN and Ti/TiN electrodes usually used for back-end of line capacitors. The access structure is a 1mA NMOS pass transistor as part of a 1T1R select.
The 16-kbit test chip in 28mn CMOS showed good performances at device level, but conditions must be tuned to deal with larger arrays. There is a clear trade-off between initial read margin and cycling endurance which was shown to be 10^8 at the cell level and about 10^4 at the array level.
The main research result was variability in the high-resistance state (HRS) which could potentially make for a problem with creating larger memory arrays without an engineering solution. The ST team has proposed a model that appears to explain the HRS spread based on tunnel barrier variation at the point where the conductive filament is closed and re-opened.
The presentation states that smaller elementary OxRAM bitcell measuring 300nm by 80nm is under evaluation in which the team will optimize the memory stack to reduce the HRS through better control of the tunnelling gap. The team is aiming for array endurance up to 10^6 cycles and data retention at 200 degrees C.
This would help Portal with the "normally-off" MCU architecture implemented in FDSOI.
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