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Semiconductors and Components

Startup Claims Quantum FinFET is World Beater

07 July 2014

FinScale Inc. (Livermore, Calif.) a startup founded by scientists and engineers including some with Russian backgrounds, has announced the availability of a technology called qFinFET, a next-generation 3D transistor the company claims can outperform conventional FinFET and SOI device technologies.

The qFinFET is available for transfer to foundries and integrated device manufacturers the company said,

The company claims that its qFinFET transistor structure is optimized for quantum effects and ballistic transport, and provides the smallest area, low leakage and high performance when compared to available advanced node FinFET and planar technology alternatives. The technology is suitable for logic and memory in the digital domain with inherent low-noise analog and RF device characteristics making it suitable as a system-on-chip platform either on bulk or SOI substrates. It is also suitable for use building stand-alone DRAM, flash and SRAM bit-cell arrays and the sense amplifiers and low-leakage pass transistors these memories require.

However, the big claim, is that the technology can be manufactured at the next-generation technology node – the 16nm/14nm node – without double-patterning. Chip manufacturers have routinely been using double-patterning lithography since the 32nm/28nm node and are striving to keep the requirement to just double-patterning at the 16nm/14nm node. An ability to make structures with just a single pass under the lithography scanner per mask, would reduce dwell times on machines and could be a significant cost saving.

"FinScale’s qFinFET offers manufacturers a high-yield 3D process for building scalable aspect-ratio fins that can be formed without double patterning down to the 14/16 nm node, providing increased performance and transistor width (W) per unit area,” said Jeffrey Wolf, FinScale CEO, in a statement. The resulting fin transistor topologies deliver area reductions, and provide designers with further area-saving and performance-boosting opportunities at the cell library and circuit level, the company said.

However, the deveolopment work to date has been theoretical. In email correspondence with Electronics 360 Wolf said: "Experimental work on silicon is pending, with device characterization test structure sets designed and design-of-experiments specified. Basic library elements are also designed; SRAM bit cells, logic macros and the like and process design-of-experiments are ready."

Build a better FinFET

"We conceived the Quantum FinFET by pushing silicon to its quantum-scaling limits, while seeking to maximize carrier mobility, electrostatic gate control, yield and reliability," said Victor Koldyaev, chief technology officer and company co-founder, in the same statement. "Using this approach we designed the qFinFET front-end-of-line (FEOL) device and process solution for the 7 and 10nm generations, and were pleased that the same device concept would significantly boost parametric performance and economic returns for manufacturers back to the 28/32nm node. We then laid out standard cells, SRAMs, eDRAMs and 2-bit/cell non-volatile memories using industry standard design rules and realized that we could readily exceed the best published results at those nodes and give manufacturers and designers opportunities for further improvement."

"FinScale has developed and patented a so-called two-dimensional self-aligned process (2DSA). The 2DSA process can be used for making 16/14 nm fins similar to a "poly-gate replacement process" similar to Intel's process, but in a simpler way that self-aligns the source and drain to the dummy gate trench and fin in two dimensions," Wolf told Electronics 360.

FinScale points out the fully-depleted silicon on insulator (FDSOI) relies on attaining a uniform channel thickness of 6nm across a 300mm-diameter wafer. At the same time established FinFET implementations have a trapezoidal cross-section, which makes for limited aspect ratios, variable performance and leakage and reduced reliability due to time-dependent dielectric breakdown susceptibility.

The self-aligned process allows single patterning to be used down to the 16nm/14nm and forming rectangular, high-aspect ratio fins, with several benefits associated with this, the company claims. These include higher Ion/Ioff ratio, higher device density, tighter threshold voltage control, lower leakage, and lower gate-to-source/drain capacitance than other FinFET implementations. And qFinFET can also be applied at 28nm and older nodes as a mid-life kicker.

"The qFinFET technology elegantly combines the advantages of current FinFET and planar FD-SOI technologies, and mitigates their inherent weaknesses to provide a unifying platform that will put the semiconductor industry back on track with Moore’s Law," said George Cheroff, a former IBM Research manager, in the same statement issued by FinScale.

So far the company has been funded by its founders and is now seeking outside investments to accelerate engagements worldwide.

Prior to founding FinScale Koldyaev spent two years with Cypress Semiconductor as a senior member of the technical staff. Before that he spent three years with Innovative Silicon Inc. where he worked on the floating-body memory technology known as ZRAM. From 1994 to 1999 Koldyaev was a visiting professor at IMEC (Leuven, Belgium) and prior to that was a group leader conducting research into advanced semiconductor device physics at Novosibirsk, Russia.

Rimma Pirogova, who serves Finscale as its chief engineer, spent 23 years between 1974 and 1997 at Novosibirsk Technical University as an associate professor, scientific fellow and senior scientific fellow with expertise in the mathematical modelling of mechanically stressed semiconductor devices between before also serving as a visiting professor at IMEC. Pirogova went on to act as a consultant to Cadence Design Systems in the United States.

Related links and articles:

www.finscale.com

News articles:

Fujitsu Backs SuVolta to Pursue DRAM, IoT

Samsung Licenses 28nm FDSOI Chip Process from ST

Samsung, Globalfoundries Form 14nm Alliance to Fight TSMC

Common Platform Preps for SOI, FinFETs at 10nm



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