Intel Corp. is collaborating with Micron Technology Inc. to provide an in-package memory for Knights Landing, latest iteration of Intel's series of prototype x86 many-core processors.
Micron is using through-silicon via (TSV) and microbumping technology utilized within its hybrid memory cube products.
Knights Landing combines high-speed logic and multiple layers of DRAM with five times the sustained memory bandwidth of DDR4, consumes one-third of the energy per bit in half the footprint.
The Xeon Phi Knights Landing plus memory component will be deployed in a Cray XC supercomputer that has been ordered by the National Energy Research Scientific Computing (NERSC) Center, Micron said.
Knights Landing is being manufactured by Intel using 14nm FinFET process technology and will include up to 72 Airmont processor cores that can work on up to four threads each.
"The next-generation Intel® Xeon Phi™ processor, codenamed Knights Landing, will launch with up to 16GB of high performance, on-package memory that delivers dramastically improved the sustained memory bandwidth versus DDR4 and brings tremendous power-efficiency and space-savings. It is the first Intel HPC processor to use this new high performance on package memory," said Charles Wuischpard, a general manager with responsibility for high performance computing at Intel, in a statement issued by Intel.
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