STMicroelectronics is investigating the use of resistive RAM as an embedded non-volatile memory at the 28nm CMOS manufacturing node.
Philippe Candelier, a memory researcher for STMicroelectronics NV at Crolles, is due to present a paper at the LETI one-day memory workshop scheduled for June 24, at Minatec, Grenoble. Candelier uses the term OxRAM in the title of his paper: Embedded OxRAM memory on 28nm CMOS process: from basic cell characteristics to statistical device performance extraction. OxRAM is a reference to RAM with a metal-oxide resistive memory element, which is most-commonly researched generic material used for resistive memory structures although the principles of operation sometimes differ and are not yet fully understood.
It remains to be seen exactly what material structure is being researched but a paper in the same session – from Jean-Michel Portal of the University of Marseille – is due to discuss an Energy friendly MCU based on OxRAM Memory for IoT Applications.
There is some evidence that the community around ST Crolles and Grenoble is turning toward hafnium-oxide (HfO2] as its metal–oxide of choice. At the Leti memory workshop in 2012 Therese Diokh, a researcher at ST, presented a study of ReRAM based on a titanium-nitride, tantalum-oxide, titanium-nitride sandwich implanted in 65nm CMOS. In 2013 Diokh had turned her study to hafnium oxide resistive RAM integrated in 65nm CMOS.
The research into ReRAM and the lack of publishing around phase-change memory embedded memory in 28nm by ST is notable because in May 2013 Jean-Marc Chery, then chief technology officer of ST, said that the company was preparing for the introduction of a 28nm bulk CMOS manufacturing process with a phase-change memory (PCM) option. The PCM would replace NOR flash memory for MCUs, as NOR is not expected to scale beyond the 40-nm node, Chery said at the time.
While PCM is compatible with the high-k metal gate bulk CMOS process it does have temperature sensitivity issues and Micron Technology Inc., the only company offering PCM commercially, has dropped the technology from its memory line up. For these reasons it is thought that the 28nm CMOS Candelier refers to is the conventional bulk planar CMOS rather than the fully-depleted, silicon-on-insulator (FDSOI) process that ST is pioneering at 28nm.
However, given ST's claims of compatibility between bulk CMOS at 28nm and FDSOI at 28nm and ease of porting of IP perhaps the development could be for both processes.
No doubt further details will emerge in June.
Related links and articles: