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Synopsys Gets OK for 16nm FinFET Design at TSMC

14 April 2014

EDA software vendor Synopsys Inc. (Mountain View, Calif.) has announced that its Galaxy EDA design flow has been "certified" by TSMC as suitable for designs aimed at TSMC's 16nm FinFET manufacturing process.

However, it remains unclear whether the certification also covers the second iteration of the 16FF process that TSMC is developing to provide equivalent performance to Intel's 14nm FinFET process (see TSMC tweaks 16nm FinFET to match Intel).

Synopsys' approval covers both cell-based design and custom design. The tools oriented towards cell-based design include: Design Compiler for synthesis, IC Compiler for physical implementation, IC Validator for physical verification, StarRC for parasitic value extraction and PrimeTime for timing analysis

The custom design tools include HSpice circuit simulation, FastSpice, CustomSim and FineSim tools, static timing analysis with NanoTime and custom implementation with the Laker custom design and layout tool.

The tools provide predictable design closure together with voltage-dependent rule checking and are the result of lengthy collaboration between TSMC and Synopsys.

"Given the complexity of dealing with 3-D transistors, we started early and significantly broadened our collaboration with Synopsys to deliver on the promise of FinFET technology. With the availability of V1.0 certified tools, all our customers can now realize the full potential of FinFET technology," said Suk Lee, TSMC senior director of design marketing, in a statement issued by Synopsys.

Related links and articles:

www.synopsys.com

www.tsmc.com

News articles:

TSMC Tweaks 16nm FinFET to Match Intel

Common Platform Preps for SOI, FinFETs at 10nm

$10 Billion Pledged for Globalfoundries in New York

IBM Chip Unit Sale Would Send Tremor Through Industry

FDSOI Gains Design Wins Amid Fab Partner Mystery



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