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Semiconductors and Components

Common Platform Preps for SOI, FinFETs at 10nm

08 April 2014

A team of engineers from IBM Microelectronics, Globalfoundries, Samsung, STMicroelectronics and UMC are due to present a 10nm logic platform that supports FinFETs on both bulk CMOS and on silicon-on-insulator wafers.

The presentation of paper 2.2 is set to be one of the highlights of the Symposium on VLSI Technology due to take place June 9 to 12 at Honolulu. It represents a coming together of the interests of the FinFET and fully-depleted silicon-on-insulator (FDSOI) camps, but not yet a complete merging.

However, FinFET structures will be the common theme in both forms of the 10nm platform and a necessary step to reducing leakage current. It could be argued that those manufacturers that will have built up experience with the FinFET at earlier nodes would be in a position to benefit faster from the 10nm logic platform.

At the 16nm node the mainstream manufacturing position is FinFET over bulk CMOS, which is pursued by Intel, TSMC, Globalfoundries, Samsung and others. In contrast STMicroelectronics has pioneered the FDSOI manufacturing process as a commercial option and signed up Globalfoundries as a potential second-source supplier.

It is notable that Globalfoundries is nominally a supporter of both the FinFET and FDSOI manufacturing variants and that the 10nm logic platform supports both styles of production.

The 10nm logic platform is intended to produce both low power and high performance circuits and offers a contacted polysilicon pitch of 64nm and a metalization pitch of 48nm for FinFETs on both bulk and SOI, according to the paper abstract. The platform is demonstrated using a specially designed SRAM bit cell, with a static noise margin of 140mV at 0.75V. The process includes multi workfunction gate stacks to provide threshold voltage tenability. The claim is that this is superior to the use of additional channel dopants as this approach increases variability.

However, whether a 10nm manufacturing process could be economically viable will depend on whether extreme ultraviolet (EUV) lithography is introduced over the next few years. The circuits reported on in this paper were prepared using 193nm wavelength immersion lithography with intensive multi-patterning and self-assembly techniques used to overcome the resolution limitations of optical lithography.

Such multipatterning serves to increase the dwell time of wafers on lithography systems. In commercial production this represents extra cost and could serve to stifle any economic advantage of moving to the smaller geometry node.

Related links and articles:

www.vlsisymposium.org

News articles:

TSMC Tweaks 16nm FinFET to Match Intel

$10 Billion Pledged for Globalfoundries in New York

IBM Chip Unit Sale Would Send Tremor Through Industry

FDSOI Gains Design Wins Amid Fab Partner Mystery

Startup Halves 28nm SRAM Power Consumption

Kalray Eyes FDSOI for Many Core Processors



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