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Memory and Storage

Startup Halves 28nm SRAM Power Consumption

31 March 2014

SureCore Ltd. (Leeds, England), a startup semiconductor IP company, has confirmed in silicon that its SRAM architecture can consume half the power of conventional SRAM designs.

The saving is based on improvements in the level sense and control circuitry but it is measured across the complete memory including the memory cell array, said Paul Wells, CEO of SureCore. In the test case this is 500-kbit array that was manufactured for SureCore by STMicroelectronics NV using its 28-nm fully depleted silicon-on-insulator (FDSOI) process.

However, the power saving is independent of process technology and applicable to bulk CMOS, FinFET and FDSOI processes. "One of the main advantages of FDSOI is the ability to use back bias to alter performance and current leakage dynamically. In the test chip we have not used back bias because we wanted to show that it is applicable to all processes," said Wells.

SureCore’s energy-efficient memory was designed using a combination of detailed circuit analysis, architectural improvements, and the use of advanced statistical models. "We looked to reduce voltage swings and minimize circuitry and came up with switched hierarchical bitline technology," said Wells.

"This is a tremendous achievement by our engineering team; right first time silicon at 28nm and performance measurements correlating exceptionally well with simulation. This demonstrates the immense capability of our technology and the expertise of our engineers to deliver next generation SRAM. Silicon verification of our design defines a major milestone in our relationships with partners and customers."

Guillaume d’Eyssautier, chairman of SureCore, commented: "These early evaluation results are excellent and show that this approach delivers game-changing power performance for emerging low power applications such as the Internet-of-Things. This performance could double battery life in power critical applications and brings the 'fit-and-forget' approach to distributed sensor networks a crucial step closer."

SureCore will target this technology, and its significant efficiency advantages, at the mobile, networking and wearable technology markets, where power is critical.

Wells added that SureCore is developing a compiler to help users integrate configurable memory arrays into their designs. "We have just begun development with an outsource engineering company and expect to be able to offer the SRAM compiler before the end of this year. The business model will still be a IP license model but the end goal is to produce 'black-box' layout files together with timing and simulation models."

Related links and articles:

www.sure-core.com

News articles:

Startup Claims SRAM Halves Power Consumption

FDSOI Gains Memory IP Support

STT-MRAM Will Hit Volume in 2014, Says Everspin

ISSCC: FDSOI Takes DSP Down to 400mV



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