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Imagination Volunteers 'Warrior' Cores for MCU Duty

27 February 2014

Having launched the Warrior Series-5 processor architecture back in October 2013 with the P5600 high-end processor core, Imagination Technologies Group plc (Kings Langley, England) is back with more Series-5 cores, the M5100 and M5150 for use in microcontrollers.

The 32-bit cores include support for hardware virtualization, a first at the MCU level Imagination claims, and are intended for use in a range of applications from the Internet of Things (IoT) up through wearable devices and automotive.

Imagination claims to have secured multiple licenses for the M51xx cores targeting automotive and other embedded processing applications. Mark Throndson, director of processor technology marketing, declined to say whether Microchip Inc. (Chandler, Arizona) is a licensee but did say: "Microchip is a MIPS MCU partner."

Mobileye NV (Amsterdam, The Netherlands), a leading supplier of image-based driver assistance systems, was a lead partner for the M51xx core and have designed it into its next design of system-on-chip for image processing. Mobileye has already shipped over 2.5 million EyeQ2 and EyeQ3 SoCs that, based on Imagination’s MIPS processor architecture, address such applications as lane departure warning, vehicle detection, pedestrian detection, intelligent headlight control and traffic sign recognition.

The M5100 integrates a real-time execution unit and SRAM controller, and is optimized for low-cost, low-power microcontroller applications. The M5150 incorporates the same execution unit as the M5100, and adds a programmable L1 instruction and data cache controller, as well as memory management support for high-performance Linux and RTOS embedded system applications.

The M51xx cores are based on the same 5-stage pipeline architecture as other Warrior cores and provide the DSP/SIMD features of the previous generation microAptiv family of cores, along with the microMIPS instruction set architecture, which provides up to 30 percent reduction in code size when compared with 32-bit only code.

The cores also feature an optional floating point unit supporting both single- and double-precision instructions.

Although the cores are fully synthesizable Imagination expects them to be aimed at process technology nodes from about 65nm down to 28nm. At 28nm the cores occupy as little as 0.04 square millimeters of silicon and as much as 0.89 square millimeters at 65nm. Similarly dynamic power consumption can be as low as 17-microwatts per megahertz.

However, the key differentiation is a hardware virtualization, which has previously been considered a high-end attribute. With virtualization, multiple, unmodified, operating systems and applications can run independently and securely at the same time.

"Imagination has seen the trends leading to the need for more advanced multi-context security and multiple execution domains right across the CPU spectrum, which is why we’re now rolling out virtualization across our entire range of MIPS Series5 CPUs, including the new entry-level M51xx family," said Tony King-Smith, executive vice president of marketing at Imagination.

Built-in prioritization mechanisms in the MIPS virtualization architecture, with support for up to seven secure/non-secure guests, enable it to optimally support real-time functionality.

In space-constrained, low-power systems such as IoT or wearable devices, virtualization could be used to implement a multiple-guest environment where one guest running a real-time kernel manages the secure transmission of sensor data, while another guest, under RTOS control, can provide the multimedia capabilities of the system. For applications that demand an even higher level of security, the new M-class cores include tamper resistant features that provide countermeasures to unwanted access to the processor operating state.

A secure debug feature increases the benefit by preventing external debug probes from accessing and interrogating the core internals.

Imagination said that several hypervisors are available or under development at Imagination and third-party hypervisor developers. Two that are available for evaluation are the Kernel-based Virtual Machine (KVM), and a microkernel hypervisor, known as Fiasco-OC, both of which are available now for the M5150 core.

Compilers are available from Mentor Graphics and Green Hills Software and operating systems supported include Linux, and various real-time operating systems including Imagination's MeOS.

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