Researchers from the CEA-Leti research institute (Grenoble, France) and STMicroelectronics NV have reported an ultra-wide voltage range digital signal processor made using a 28nm fully depleted silicon on insulator (FDSOI) manufacturing process.
The paper, “A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding Fmax Tracking,” was presented on Wednesday (Feb. 12), during Session 27 of the International Solid-State Circuits Conference, held in San Francisco.
One of the keys to energy-efficient electronics is to operate ICs with reasonable performance at the lowest voltage possible. However, usually as the voltage reduces the maximum attainable clock frequency reduces to zero. The clock frequency of 460MHz, achieved at an operating voltage of 400mV, is a factor of ten higher than previously achieved at such a low voltage, Leti claims.
The FDSOI process is also able to achieve high performance at conventional voltages – 2.6GHz at 1.3V. It therefore provides a platform that allows developers to build processors that can be operated more flexibly using dynamic voltage and frequency scaling (DVFS) than alternative processes. However, alternative processes such as planar and FinFET CMOS are the preferred manufacturing options of the major chipmakers and foundries.
ST's DSP device includes body-bias-voltage scaling from 0V to +2V that helps decreases minimum circuit operating voltage. In addition ST and Leti developed standard cells libraries that are characterized over the range from 275mV to 1.2V. Among the optimized cells, fast pulse-triggered flip-flops are designed for variability tolerance at low voltage. Additionally, on-chip timing-margin monitors dynamically adjust the clock frequency to a few per cent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology.
"This demonstration DSP shows that FDSOI is blazing the trail for better portable and battery-powered products, using more efficient semiconductor chips, all the way down to the 10nm node," said Philippe Magarshack, executive vice president of design enablement services for STMicroelectronics, in a statement issued by Leti.
A demonstration kit was shown to attendees that allows body-bias to be altered the self-optimization for frequency to be followed.
Thierry Collette, head of the design and embedded systems platform, at Leti, said that the component could ultimately be suitable for Internet-of-Things end products. The DSP design that has been implemented comes from Leti and is of a classical 32bit architecture of about 200kgates complexity, said Fabien Clermidy, head of Leti's digital design and architecture lab. He added that the jointly developed FDSOI libraries would allow the device to operate down to 300mV although memory performance becomes critical at such voltages.
Although the DSP was developed as a Leti research project Clermidy said it is possible that the design could transfer into commercial manufacture now that it has been proved in FDSOI silicon.
Related links and articles: