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The Cost of Escalating R&D

03 December 2013

The electronics industry laments the rising cost of designing electronics. That cost, I hasten to add, will continue to rise as the market's appetite for more complex and sophisticated electronics increases unabated … unless we do things differently.

Plenty of thought and brain power has gone into attempting to address these costs. I am a firm believer that raising the level of abstraction of design is a key element in the cost-reduction process. However, I also believe that many engineers and engineering managers misunderstand both the magnitude and nature of the value that more abstract high-level design can bring to bear on this problem. When engineering managers discuss the benefits of high-level design, most think "productivity" and assume that this productivity is only realized during the initial design of new custom logic.

I beg to differ. While this process is a benefit, the most significant long-term benefit is actually in the form of the newly created IP and not the process used to create it. High-level IP –– that is, IP created at the behavioral level of design –– is inherently more flexible and re-targetable than low-level IP. Investing in the creation of IP in this form will yield value in both performance and quality of result (QoR) for many years to come.

Evolving value recognition

Savvy engineering managers have already recognized the value of high-level design, though that recognition is evolving. They cite impressive results, noting that their engineering teams see an immediate three-to-five times productivity improvement when they move to high-level design.

Remarkably, one manager recognized what his engineering team had created was so much more valuable and offered greater longevity than those designs that were started from scratch. He calculated that these designs offered even more value three years later––20X productivity improvement due to the inherent superiority of retargeting abstract IP over traditional register transfer level (RTL) IP.

One large electronics company's engineering manager went a step further, assigning the engineering team the task of redesigning his team's IP portfolio. Rather than simply reusing their existing RTL IP for a new project at a new technology node, the engineers rewrote the existing RTL code in behavioral form. They then targeted the behavioral IP at the new technology node with new performance constraints. Not only was this approach faster for the current project, but they now had their IP in a much more flexible form that would be reusable for many years to come.

That's what I call enlightened reuse.

Eliminating the Time Domain

One of the most important benefits of behavioral design is that it allows the designer to minimize or even eliminate consideration of the time domain. By this, I mean the designer does not need to consider where one clock cycle ends and another begins. High-level synthesis tools take care of this automatically. The benefit of this approach is that a designer can focus on the functionality and features of the design. The high-level synthesis tool takes the clock speed as an input, and is able to, for example, produce one design at 100 megahertz and another at 500MHz with no modification of the design.

Clearly, there is a learning curve associated with moving to a higher level of abstraction in the same way that designers were challenged to change the way they thought during the transition from gate-level design to RTL design. More and more designers are taking up the new challenge and are bringing significant benefit to their organizations by creating IP that is simply worth more than RTL IP.

Sean Dart is CEO of Forte Design Systems, a provider of electronic system-level synthesis software.

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