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Processors

Processors Focus on Data Center at ISSCC

07 November 2013

Processors for servers and data centers will dominate Session 5 at the 2014 International Solid-State Circuits Conference (ISSCC) in San Francisco in February.

While Intel versus ARM—in the form of papers on a high-end Xeon chip from Intel and the X-Gene 64-bit ARM processor from Applied Micro—may capture popular interest, IBM has no fewer than three papers scheduled on aspects of its Power8 architecture processors with interesting technical achievements.

Intel's paper introduces an Ivytown Xeon processor containing 15 cores and 37.5 megabytes (MB) of shared L3 cache. Implemented in 22-nm high-k metal gate tri-gate (FinFET) CMOS with nine metal layers, the chip has a transistor count of 4.31 billion. It features a ring-bus topology for its cores, according to an abstract of the ISSCC paper released by the organizers. It includes multiple phase-locked loops (PLLs) for clocking on a one-per-column basis.

Applied Micro's paper will detail X-Gene, which is aimed at micro-server applications. X-Gene is an implementation of the ARMv8 instruction set architecture and its 64-bit capability. In contrast to the Intel processor, the ARM SoC is implemented in a relatively modest 40-nm manufacturing process and includes eight cores running at up to 3.0GHz clock frequency. However, the abstract tips that X-Gene comprises four pairs of cores, suggesting strongly that X-Gene is implementing a form of big-little architecture. The fact that the chip operates at 0.9V and consumes 4.5W also attests to the importance of energy efficiency in data center and server applications.

Power8 is the latest manifestation of the Power architecture from IBM and is designed to support massively multi-threaded chips with large amounts of embedded DRAM cache. IBM has manufactured the chip in its 22-nm silicon-on-insulator (SOI) gate-first process with 15 levels of metal, putting it on a par with Intel.

The chip includes 12 cores and 96 MB of on-chip L3 cache and features 7.6 terabits per second of off-chip bandwidth, integrated voltage regulation and resonant clocking.

The clocking scheme, described in a separate paper, has the ability to oscillate from 2.5 GHz to greater than 5 GHz and can dynamically switch between high and low resonant frequency modes without idle cycles. The multi-mode resonant design reduces clock grid power consumption by 33 percent.

It remains to be seen whether the resonant clocking is of IBM's own design or is based on a license from Cyclos Semiconductor Inc. (Berkeley, Calif.). Cyclos is a startup with expertise in this area, having won a design in with Advanced Micro Devices reported at ISSCC 2012. AMD's Piledriver 64-bit core, fabricated in a 32-nm CMOS process, achieves clock frequencies of 4GHz.

In this ISSCC, AMD will provide further details of Steamroller, a high-end x86 core that is a follow-on to Piledriver implemented in 28-nm CMOS.

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