Do you remember Deep Blue? In 1997, the one-and-a-half ton IBM supercomputer defeated chess master Garry Kasparov in several games. Deep Blue had the computing power of almost 12 GFLOPS (Giga Flops, or 12x109 floating-point calculations per second). Fifteen years later, that iPhone 4S you hold in your hand has 16 GFLOPS.
In 2011, IBM’s next generation supercomputer named “Watson” defeated two of the best Jeopardy players ever. That machine has 15 terabytes (TB) of memory and almost 3,000 processors, with a total computing power of 10 TFLOPS (10 Tera Flops, or 12x1012 floating-point calculations per second). How will we in 15 years achieve Watson’s computing power in a hand-held device?
Conventional wisdom says we’ll do it by “scaling.” Scaling is an incremental process of reducing the size of transistors that results in improvements in their performance. By decreasing the dimensions of a MOSFET transistor by a factor of two, its voltage drops by two, its speed increases by two, and the circuit area, power and cost all drop by 22.
For decades now, every 18 to 24 months we have been doubling the number of transistors in a chip. That is, reducing their size by a factor of two. This is Moore's Law, coined by Gordon Moore, the co-founder of Intel Corp. It has been inviolate for over six decades.
The latest generation of semiconductor device has scaled down to a node size of 22 nanometers (nm). The node size is the smallest feature in a transistor, normally the gate. The International Technology Roadmap for Semiconductors (ITRS), produced by the Semiconductor Industry Association (SIA), predicts that the 8 nm node will be achievable by 2018.
At a crossroads
The problem with the conventional wisdom of scaling – and Moore’s Law – is that it’s running out of gas. The semiconductor industry has almost reached the limit at which lithography can be used in the normal way. It has not yet been able to develop the extreme ultraviolet (EUV) technology for which the industry has been waiting for years. As the industry pushes toward nodes sizes below 22 nm, conventional single-exposure lithography will no longer be useful.
Today, the industry is at a crossroads. We have found that scaling beyond the 22 nm node will require architectural and material changes in traditional MOSFETs for efficient operation of the transistor.
The challenge is to scale the gate oxide in MOSFETs beyond the 1.0 - 1.5 nm. At these dimensions, electrons can easily tunnel through such thin insulators. According to ITRS, a 1 nm oxide thickness will be required in MOS devices with lateral dimensions in the order of 50 nm. At these dimensions, it is extremely difficult to keep the depletion regions associated with PN junctions from interacting with each other, hence defeating the purpose of the junction.
It is interesting to look back at what we have accomplished to understand what changes and adjustments are needed to continue scaling devices for profitability – a necessary condition – and performance. Stanford Professors James D. Plummer, Michael D. Deal and Peter B. Griffin describe the stages of these changes in their book “Silicon VLSI Technology.” They divide scaling into three intervals as shown in the chart below and described briefly here:
· 1960 – 2002. The era of simple scaling, where pure lithography could accomplish the task. The main problem encountered at the end of this era was that as feature size decreased, conductors became too resistive. The solution to this problem was to replace aluminum in the vias with copper.
· 2002 – 2018. Scaling alone is not sufficient here, innovation is required. This includes computational lithography: “strained silicon”; hi-K metal gates; and tri-gate transistors and other 3D packaging technologies. At the same time, the industry is working on nano-devices and new materials for the channels and gates of transistors. However, the most important revolutionary change being explored now is the replacement of the channel with a combination of materials from the III-IV columns of the periodic table.
· Beyond 2018. To go beyond 2018, the industry will have to invent new technologies and materials. The most promising area of research is in nano-electronics, where carbon-based materials are being developed to design transistors of the future.
What comes after 2018?
Nano-electronics is broadly defined as the science that will allow us to manipulate matter on dimensions of less than 100 nm, to create structures with electronic properties that can be useful to develop practical devices. The nano-electronics revolution is on a fast track now, but not as fast as the semiconductor industry requires. As a consequence, the flood gates have been opened to fund research that will enable the industry to break through the 2018 barrier.
This research is focusing on graphene-based electronics, molecular-organic electronics, single-electron transistors, nanotubes and silicon nanowires. Researchers, using these materials, are developing (and using) innovative approaches based on the aforementioned techniques and materials, with the idea that in the near future we can change the very nature of electronics.
Among the new materials and techniques, there are three that will enable us to break through the barrier and, at the same time, change the very nature of how we define electronics:
· Graphene. This material has gained a tremendous attention. Prototype structures and simulations of transistors have been developed using grapheme including graphene nanoribbon MOSFET (GNRFET), bilayer graphene nanoribbon MOSFET (BGNFET), tri-layer graphene nanoribbon MOSFET (TGNFET) and other structures.
· Carbon nanotubes. Due to the electrical characteristics of the cylinder of graphene, researchers have developed the carbon-nanotube field effect transistor (CNTFET), a transistor similar to the silicon-based technology with the channel replaced by a nanotube.
· Silicon nanowire (SiNW). This is an elongated, crystalline or amorphous silicon wire with a diameter ranging from 10 nm to 100 nm. Even if these wires are made of silicon, they have properties significantly different from bulk silicon. At nanoscale dimensions, materials behave differently due to the quantum effects that take over the Newtonian physics.
Nano-electronics have the potential in numerous applications; however, there are technical and economic obstacles for commercialization. One is the long time period required from research to development, according to Professor Sohail Anwar, a researcher at Penn State University. This gap, he said, must be addressed by industry, government and academia.
Collaboration, collaboration, collaboration
A prime example of the type of collaboration Anwar is calling for is a program created by the National Science Foundation (NSF) called the National Nanotechnology Infrastructure Network (NNIN). This is an integrated network of universities, government agencies and industries with the purpose of sharing facilities and resources (including human resources) for the ultimate goal of breaking through the 2018 wall. The NNIN offers open access, to any user, to leading-edge nanotechnology tools, capabilities for fabrication, synthesis, simulation, design and integration.
The scope of the technical research at the NNIN includes nano-electronics, optics, optoelectronics, MEMS and other subjects related to nano-electronics. The members of the NININ include the NSF, the Nanoelectronics Research Initiative (NRI, a Federal agency), nanoHub at Purdue University, Cornell University, MIT, Penn State, Harvard’s Center of Nanoscale Systems (CNS) and others.
Corporations are slowly realizing, too, that to develop technologies for post-2018, they will have to join forces and work together to develop the technology of the future. A recent example of this special collaboration is the creation of the 450-mm consortium at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York. This research consortium is comprised, among others, of IBM, Globalfoundries, TSMC, Applied Materials, Tokyo Electrons (TEL) and Sematech International. They are working together to develop technologies for the 450-mm fabrication techniques and beyond, something that would have been unthinkable just a few years ago.
Initiatives such as NNIN and CNSE hold the key to the post-2018 world of electronics. And the clock is ticking.